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NCV8509 Series
Sequenced Linear
Dual-Voltage Regulator
The NCV8509 Series are dual voltage regulators whose output
voltages power up in such a manner as to protect the integrity of
modern day microcontroller I/O and ESD input structures. Newer
generation microcontrollers require two power supplies. One voltage
is used for powering the core, while the other powers the I/O.
Features
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SOIC 16 LEAD
WIDE BODY
EXPOSED PAD
PDW SUFFIX
CASE 751AG
•
Power−Up Sequence
•
Output Voltage Options:
♦
16
1
•
•
•
•
•
•
•
•
•
•
•
V
OUT1
5 V (±2%) 115 mA, V
OUT2
2.6 V (2%) 100 mA
♦
V
OUT1
5 V (±2%) 115 mA, V
OUT2
2.5 V (2%) 100 mA
♦
V
OUT1
3.3 V (±2%) 115 mA, V
OUT2
1.8 V (2%) 100 mA
Low 175
mA
Quiescent Current
Power Shunt
Programmable RESET Time
Dual Drive RESET Valid
Programmable SLEW Rate Control
Thermal Shutdown
16 Lead SOW Exposed Pad
NCV Prefix, for Automotive and Other Applications Requiring Site
and Change Control
AEC Qualified
PPAP Capable
Pb−Free Packages are Available
MARKING DIAGRAM
16
NCV8509xx
AWLYYWWG
1
xx
Below:
= Voltage Ratings as Indicated
26 = 5 V/2.6 V
25 = 5 V/2.5 V
18 = 3.3 V/1.8 V
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Device
Typical Applications
•
Automotive Powertrain
•
Telematics
MRA4004T3
V
IN1
C
IN1
10
μF
V
BAT
R
EX
138
Ω
C
IN2
0.1
μF
V
OUT1
V
OUT2
C
VOUT1
10
μF
Microprocessor
C
VOUT2
10
μF
R
RESET
10 k
C
SLEW
33 nF
A
WL
YY
WW
G
PIN CONNECTIONS
SLEW
Delay
GND
NC
NC
RESET
NC
NC
1
16
NC
V
OUT1
NC
V
IN1
V
IN2
NC
V
OUT2
NC
V
IN2
NCV8509
SLEW
RESET
Delay
GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
C
Delay
33 nF
Figure 1. Application Diagram
©
Semiconductor Components Industries, LLC, 2008
June, 2008
−
Rev. 24
1
Publication Order Number:
NCV8509/D
NCV8509 Series
MAXIMUM RATINGS
Rating
V
IN1
(dc)
V
IN1
Peak Transient Voltage
V
IN2
(dc)
V
IN2
(Current out of pin)
Operating Voltage
Input Voltage Range (SLEW, RESET, Delay)
V
OUT1
V
OUT2
Electrostatic Discharge (Human Body Model)
(Machine Model)
Package Thermal Resistance, SOW−16 E Pad:
Lead Temperature Soldering:
Junction−to−Case, R
θJC
Junction−to−Ambient, R
θJA
Reflow: (SMD styles only) (Note 1)
Value
−0.3
to 50
50
50
10
50
−0.3
to 10
10
10
4.0
400
16
57
240 peak (Note 2)
Unit
V
V
V
mA
V
V
V
V
kV
V
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. 60 second maximum above 183°C.
2.
−5°C/+0°C
allowable conditions.
ELECTRICAL CHARACTERISTICS
(6.0 V < V
IN1
< 18 V, I
VOUT1
= 5.0 mA, I
VOUT2
= 5.0 mA,
−40°C
< T
J
< 125°C,
C
VOUT1
= C
VOUT2
= 10
mF;
unless otherwise noted.)
Characteristic
V
OUT1
Output Voltage
5 V Option
3.3 V Option
Dropout Voltage (V
IN1
−
V
OUT1
)
Load Regulation
Line Regulation
Current Limit
V
OUT2
Output Voltage
2.6 V Option
2.5 V Option
1.8 V Option
Load Regulation
Line Regulation
Current Limit
General
Quiescent Current
Thermal Shutdown (Note 3)
3. Both outputs will turn off.
I
OUT1
= I
OUT2
= 100
μA,
V
IN1
= 12 V
I
OUT1
= I
OUT2
= 50 mA, V
IN1
= 14 V
(Guaranteed by Design)
−
−
150
125
5.0
180
175
10
210
μA
mA
°C
1.0 mA < I
VOUT2
< 100 mA
1.0 mA < I
VOUT2
< 100 mA
1.0 mA < I
VOUT2
< 100 mA
1.0 mA < I
VOUT2
< 100 mA
6.0 V < V
IN1
= V
IN2
< 18 V
V
OUT2
= V
OUT2
(typ)
−
500 mV
V
OUT2
= 0 V
2.548
2.450
1.764
−
−
105
−
2.6
2.5
1.8
5.0
10
305
105
2.652
2.550
1.836
50
50
610
300
V
V
V
mV
mV
mA
mA
1.0 mA < I
VOUT1
< 100 mA
1.0 mA < I
VOUT1
< 100 mA
I
OUT
= 100 mA
I
OUT
= 100
μA
1.0 mA < I
VOUT1
< 100 mA
6.0 V < V
IN1
< 18 V
V
OUT1
= V
OUT1
(typ)
−
500 mV
V
OUT1
= 0 V
4.9
3.234
−
−
−
−
115
−
5.0
3.3
400
100
10
10
305
105
5.1
3.366
600
200
50
50
610
300
V
V
mV
mV
mV
mV
mA
mA
Test Conditions
Min
Typ
Max
Unit
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2
NCV8509 Series
ELECTRICAL CHARACTERISTICS
(continued)
(6.0 V < V
IN1
< 18 V, I
VOUT1
= 5.0 mA, I
VOUT2
= 5.0 mA,
−40°C
< T
J
< 125°C,
C
VOUT1
= C
VOUT2
= 10
mF;
unless otherwise noted.)
Characteristic
SLEW
SLEW Charging Current
V
OUT1
SLEW Rate (Note 4)
5 V Option
3.3 V Option
V
OUT2
SLEW Rate
2.6 V Option
2.5 V Option
1.8 V Option
SLEW Control Threshold
RESET
RESET Threshold Increasing
(Note 5)
RESET Threshold Decreasing
5 V Option
3.3 V Option
2.6 V Option
2.5 V Option
1.8 V Option
RESET Output Low
RESET Output Peak
RESET Threshold Hysteresis
5 V Option
3.3 V Option
2.6 V Option
2.5 V Option
1.8 V Option
Delay
Delay Switching Threshold
Delay Charge Current
Delay Saturation Voltage
Delay Discharge Current
Output Tracking
Delta 1 [V
OUT1
−
V
OUT2
]
5 V Option
3.3 V Option
Delta 2 [V
OUT2
−
V
OUT1
]
Power Shunt
Shunt Voltage 1 (V
IN2
)
Shunt Voltage 2 (V
IN2
)
V
IN1
= 6.0 V, I
OUT2
= 100 mA, No R
EX
V
IN1
= 12 V, 1.0 mA < I
OUT2
< 100 mA, No R
EX
3.3
3.25
−
4.5
4.6
5.75
V
V
C
OUT1
= C
OUT2
, I
OUT1
= I
OUT2
C
OUT1
= C
OUT2
, I
OUT1
= I
OUT2
C
OUT1
= C
OUT2
, I
OUT1
= I
OUT2
−
−
−
−
−
−
3.2
2.8
100
V
V
mV
Delay = 1.0 V
V
OUT1
Out of Regulation
Delay = 5.0 V V
OUT1
out of Regulation
−
1.125
4.0
−
10
1.5
6.0
−
−
1.875
8.0
0.1
−
V
μA
V
mA
I
RESET
= 1.0 mA
Power Down (See Figure 41)
−
50
33
26
25
18
100
66
52
50
36
150
99
78
75
54
mV
mV
mV
mV
mV
−
−
4.5
2.97
2.34
2.25
1.62
−
−
4.73
3.12
2.46
2.36
1.70
0.1
0.6
0.965
×
V
OUT
0.965
×
V
OUT
0.965
×
V
OUT
0.965
×
V
OUT
0.965
×
V
OUT
0.4
1.0
V
V
V
V
V
V
V
94.5
96.5
98.5
%
SLEW = 1.0 V
C
SLEW
= 33 nF
−
−
C
SLEW
= 33 nF
−
−
−
(See Figure 53)
1.5
370
355
256
1.8
−
−
−
2.1
V/s
V/s
V/s
V
710
469
−
−
V/s
V/s
4.0
6.0
8.0
μA
Test Conditions
Min
Typ
Max
Unit
4. Not a tested parameter.
5. RESET signal sensitive to V
OUT1
and V
OUT2
.
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3
NCV8509 Series
PIN DESCRIPTION
Pin No.
1
2
3
Symbol
SLEW
Delay
GND
NC
Description
Control for output rise time during power up. Requires capacitor to ground.
Timing capacitor for RESET function.
Ground.
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Á
Á
4, 5, 7−9, 11, 14, 16
6
No connection.
RESET
V
OUT2
V
IN2
V
IN1
Active reset (accurate to V
OUT
> 1.0 V).
Input voltage for V
OUT2
.
10
12
13
15
100 mA output (±2% output voltage) for powering microprocessor core.
Input voltage for V
OUT1
, and internal circuitry.
V
OUT1
100 mA output (±2% output voltage) for powering microprocessor I/O.
V
IN1
C
IN1
V
REF
R
EX
SLEW
Control
V
IN2
C
IN2
Power Shunt
V
BG
V
REF
V
IN1
+
+
+
−
SLEW
C
SLEW
V
OUT1
Error Amp
V
REF
C
OUT1
Start−Up
Current
+
−
Bandgap
& Bias
GND
−
+
V
OUT1
V
IN1
RESET
V
OUT1
V
BG
Delay
Discharge
Latch
−
+
V
REF
RESET Comp
Delay
C
Delay
+
+
+
−
V
IN2
Thermal
Shutdown
V
OUT2
Error Amp
V
REF
C
OUT2
Start−Up
Current
Figure 2. Block Diagram
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