KM68S1000E Family
Document Title
128Kx8 bit Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0.0
1.0
History
Initial draft
Finalize
Draft Data
September 10, 1998
April 12, 1999
Remark
Preliminary
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.0
April 1999
KM68S1000E Family
128Kx8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
•
Process Technology: TFT
•
Organization: 128Kx8
•
Power Supply Voltage: 2.3V ~ 2.7V
•
Low Data Retention Voltage: 2V(Min)
•
Three state output and TTL Compatible
•
Package Type: 32-TSOP1-0820F, 32-TSOP1-0813.4F
CMOS SRAM
GENERAL DESCRIPTION
The KM68S1000E families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
industrial operating temperature ranges and have various
package types for user flexibility of system design. The fami-
lies also support low data retention voltage for battery back-up
operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature Vcc Range
Speed(ns)
Standby
(I
SB1
, Max)
10µA
Operating
(I
CC2,
Max)
15mA
PKG Type
32-TSOP1-0820F
32-TSOP1-0813.4F
KM68S1000ELI-L
Industrial(-40~85°C)
2.3~2.7V
85
1)
/100
1. The parameters are tested with 30pF test load
PIN DESCRIPTION
A11
A9
A8
A13
WE
CS2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
32-TSOP
32-
S
TSOP
Type1-Forward
Row
select
Memory array
1024 rows
128×8 columns
Name
A
0
~A
16
WE
CS
1
,CS
2
OE
I/O
1
~I/O
8
Vcc
Vss
N.C.
Function
Address Inputs
I/O
1
Write Enable Input
Chip Select Input
Output Enable Input
Data Inputs/Outputs
Power
Ground
No Connection
CS
1
CS
2
WE
OE
I/O
8
Data
cont
I/O Circuit
Column select
Data
cont
Control
logic
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 1.0
April 1999
KM68S1000E Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
Function
CMOS SRAM
KM68S1000ELTI-8L
KM68S1000ELTI-10L
KM68S1000ELTGI-8L
KM68S1000ELTGI-10L
32-TSOP F, 85ns, 2.5V
32-TSOP F, 100ns, 2.5V
32-sTSOP F, 85ns, 2.5V
32-sTSOP F, 100ns, 2.5V
FUNCTIONAL DESCRIPTION
CS
1
H
X
1)
L
L
L
CS
2
X
1)
L
H
H
H
OE
X
1)
X
1)
H
L
X
1)
WE
X
1)
X
1)
H
H
L
I/O
High-Z
High-Z
High-Z
Dout
Din
Mode
Deselected
Deselected
Output Disabled
Read
Write
Power
Standby
Standby
Active
Active
Active
1. X means don′t care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
Ratings
-0.5 to V
CC
+0.5
-0.3 to 4.0
1.0
-65 to 150
-40 to 85
Unit
V
V
W
°C
°C
Remark
-
-
-
-
KM68S1000ELI
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.0
April 1999
KM68S1000E Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Product
KM68S1000E Family
All Family
KM68S1000E Family
KM68S1000E Family
Min
2.3
0
2.0
-0.3
3)
CMOS SRAM
Typ
2.5
0
-
-
Max
2.7
0
Vcc+0.3
0.6
Unit
V
V
V
V
Note:
1. T
A
=-40 to 85°C, otherwise specified
2. Overshoot : Vcc+1.0V in case of pulse width≤20ns
3. Undershoot : -1.0V in case of pulse width≤20ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
1
)
(f=1MHz, TA=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Average operating current
Output low voltage
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
V
OL
V
OH
I
SB
I
SB1
V
IN
=Vss to Vcc
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL
, Read
Cycle time=1µs, 100%duty, I
IO
=0mA, CS
1
≤0.2V,
CS
2
≥Vcc-0.2V,
V
IN
≤0.2V
Cycle time=Min, 100% duty, I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL
Test Conditions
Min Typ Max Unit
-1
-1
-
-
-
-
2.0
-
-
-
-
-
-
-
-
-
-
0.2
1
1
1
2
15
0.4
-
0.3
10
µA
µA
mA
mA
mA
V
V
mA
µA
I
OL
=0.5mA
I
OH
=-0.5mA
CS
1
=V
IH
, CS2=V
IL
, Other inputs=V
IH
or V
IL
CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V
or CS
2
≤0.2V,
Other inputs=0~Vcc
4
Revision 1.0
April 1999
KM68S1000E Family
AC OPERATING CONDITIONS
TEST CONDITIONS
( Test Load and Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
Input and output reference voltage :1.1V
Output load(see right) : C
L
=100pF+1TTL
C
L
=30pF+1TTL
C
L
1)
CMOS SRAM
1. Including scope and jig capacitance
AC CHARACTERISTICS
(V
CC
=2.3~2.7V, T
A
=-40 to 85°C
)
Speed Bins
Parameter List
Symbol
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Read
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
t
RC
t
AA
t
CO1
, t
CO2
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
85
-
-
-
10
5
0
0
10
85
70
0
70
60
0
0
35
0
5
85ns
Max
-
85
85
40
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
100ns
Min
100
-
-
-
10
5
0
0
15
100
80
0
80
70
0
0
40
0
5
Max
-
100
100
50
-
-
30
30
-
-
-
-
-
-
-
30
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
V
DR
I
DR
t
SDR
t
RDR
CS
1
≥Vcc-0.2V
1)
Vcc=2.5V, CS
1
≥Vcc-0.2V
1)
See data retention waveform
Test Condition
Min
2.0
-
0
5
Typ
-
0.2
-
-
Max
2.7
10
-
-
Unit
V
µA
ms
1. CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V(CS
1
controlled) or CS
2
≤0.2V(CS
2
controlled)
5
Revision 1.0
April 1999
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