Data Sheet, Rev. 1.4, Apr. 2006
HYS64T16000HU–[3.7/5]–A
HYS72T32000HU–[2.5/25F/3/3S/3.7/5]–A
HYS64T32001HU–[2.5/25F/3/3S/3.7/5]–A
HYS[64/72]T64020HU–[2.5/25F/3/3S/3.7]–A
240-Pin Unbuffered DDR2 SDRAM Modules
DDR2 SDRAM
UDIMM SDRAM
RoHs Compliant
Memory Products
Edition 2006-04
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
©
Infineon Technologies AG 2006.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
HYS64T16000HU–[3.7/5]–A, HYS72T32000HU–[2.5/25F/3/3S/3.7/5]–A, HYS64T32001HU–
[2.5/25F/3/3S/3.7/5]–A, HYS[64/72]T64020HU–[2.5/25F/3/3S/3.7]–A
Revision History:
2006-04,
Rev. 1.4
Page
Subjects (major changes since last revision)
Product portfolio extended : Added -2.5F and -3.7 products
Chapter 1.1 Added features for average self refresh and self refresh rate to Feature list
Chapter 3
Chapter 3
Chapter 4
Chapter 4
Chapter 5
Updated
I
DD
Currents
Corrected note 4 - Table 18
Updated SPD Codes
SPD Codes update: Byte 49 Bit 0 = 1 (HighT_SRFEntry) for all product types
Package Outlines updated
Updated Product type definition
I
DD
currents updated
SPD Codes updated
Previous Revision: 2005-09, Rev. 1.3
Previous Revision:2005-05 Rev. 1.2
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send us your proposal (including a reference to this document) to:
techdoc.mp@infineon.com
Template: mp_a4_s_rev321 / 3 / 2005-10-05
HYS[64/72]T[16/32/64]0xxHU–[2.5/../5]–A
Unbuffered DDR2 SDRAM Modules
Table of Contents
Table of Contents
1
1.1
1.2
2
2.1
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2
4
5
6
Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration and Block Diagrams
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Electrical Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
DD
Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
DD
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
26
26
27
27
29
37
38
43
45
SPD Codes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Package Outlines
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Data Sheet
4
Rev. 1.4, 2006-04
02182004-DHQB-4RRW
240-Pin Unbuffered DDR2 SDRAM Modules
DDR2 SDRAM
HYS64T16000HU–[3.7/5]–A
HYS72T32000HU–[2.5/25F/3/3S/3.7/5]–A
HYS64T32001HU–[2.5/25F/3/3S/3.7/5]–A
HYS[64/72]T64020HU–[2.5/25F/3/3S/3.7]–A
1
Overview
This chapter gives an overview of the 1.8 V 240-Pin Unbuffered DDR2 SDRAM Modules product family and
describes its main characteristics.
1.1
•
Features
•
•
•
•
•
•
•
•
•
•
Programmable CAS Latencies (3, 4, 5 and 6), Burst
Length (4 & 8) and Burst Type
Auto Refresh (CBR) and Self Refresh
Average Refresh Period 7.8 µs at a
T
CASE
lower
than 85 °C, 3.9 µs between 85 °C and 95 °C
Programmable self refresh rate via EMRS2 setting
All inputs and outputs SSTL_18 compatible
Off-Chip Driver Impedance Adjustment (OCD) and
On-Die Termination (ODT)
Serial Presence Detect with E
2
PROM
UDIMM Dimensions (nominal):
30 mm high, 133.35 mm wide
Based on standard reference layouts Raw Card “A”,
“C”, “D“, “E“, “F” and “G”
RoHS compliant products
1)
•
•
•
•
240-Pin PC2–6400, PC2–5300, PC2–4200 and
PC2–3200 DDR2 SDRAM memory modules for use
as main memory when installed in systems such as
mobile personal computers.
16M
×
64, 32M
×
64, 32M
×
72, 64M
×
64,
64M
×
72 module organization and 16M
×
16,
32M
×
8 chip organization
128 MB, 256 MB and 512 MB modules built with
256-Mbit DDR2 SDRAMs in PG-TFBGA-60 and
PG-TFBGA-84 chipsize packages
Standard Double-Data-Rate-Two Synchronous
DRAMs (DDR2 SDRAM) with a single + 1.8 V
(± 0.1 V) power supply
All Speed Grades faster than DDR2–400 comply
with DDR2–400 timing specifications
Performance for PC2–6400
–2.5F
PC2–6400 5–5–5
@CL6
f
CK6
400
@CL5
f
CK5
400
@CL4
f
CK4
266
@CL3
f
CK3
200
Table 1
Product Type Speed Code
Speed Grade
max. Clock Frequency
–2.5
PC2–6400 6–6–6
400
333
266
200
15
15
45
60
Unit
—
MHz
MHz
MHz
MHz
ns
ns
ns
ns
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
t
RCD
t
RP
t
RAS
t
RC
12.5
12.5
45
57.5
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic
equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January
2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and
polybrominated biphenyl ethers.
Data Sheet
5
Rev. 1.4, 2006-04
02182004-DHQB-4RRW
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