DATASHEET
HM-6514/883
1024 x 4 CMOS RAM
FN2996
Rev.1.00
March 1997
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby . . . . . . . . . . . . . . . . . . . 125W Max
• Low Power Operation. . . . . . . . . . . . . . 35mW/MHz Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
• TTL Compatible Input/Output
• Common Data Input/Output
• Three-State Output
• Standard JEDEC Pinout
• Fast Access Time . . . . . . . . . . . . . . . . . . 120/200ns Max
• 18 Pin Package for High Density
• Gated Inputs - No Pull Up or Pull Down Resistors
Required
• On-Chip Address Register
Description
The HM-6514/883 is a 1024 x 4 static CMOS RAM fabri-
cated using self-aligned silicon gate technology. The device
utilizes synchronous circuitry to achieve high performance
and low power operation.
On chip latches are provided for addresses allowing efficient
interfacing with microprocessor systems. The data output
can be forced to a high impedance state for use in expanded
memory arrays.
Gated inputs allow lower operating current and also eliminates
the need for pull up or pull down resistors. The HM-6514/883 is
fully static RAM and may be maintained in any state for an
indefinite period of time.
Data retention supply voltage and supply current are guaran-
teed over temperature.
Ordering Information
120ns
HM1-6514S/883
200ns
HM1-6514B/883
300ns
HM1-6514/883
TEMPERATURE RANGE
-55
o
C to 125
o
C
PACKAGE
CERDIP
PKG. NO.
F18.3
Pinout
HM-6514/883
(CERDIP)
TOP VIEW
A6
A5
A4
A3
A0
A1
A2
E
GND
1
2
3
4
5
6
7
8
9
18 VCC
17 A7
16 A8
15 A9
14 DQ0
13 DQ1
12 DQ2
11 DQ3
10 W
PIN
A
E
W
D
Q
DESCRIPTION
Address Input
Chip Enable
Write Enable
Data Input
Data Output
FN2996 Rev.1.00
March 1997
Page 1 of 9
HM-6514/883
Functional Diagram
LSB A9
A8
A7
A6
A5
A4
A
LATCHED
ADDRESS
REGISTER A
L
L
LSB A2
A1
A0
A3
A
LATCHED
ADDRESS
REGISTER
4
A
4
E
W
DQ
G
6
GATED
ROW
DECODER
64 x 64
MATRIX
64
6
G
16 16 16 16
GATED
COLUMN
I/O SELECT
4
1 OF 4
FN2996 Rev.1.00
March 1997
Page 2 of 9
HM-6514/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance
CERDIP Package . . . . . . . . . . . . . . . .
15
o
C/W
o
C to +150
o
C
Maximum Storage Temperature Range . . . . . . . . .-65
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300
o
C
75
o
C/W
JA
JC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range. . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VCC -2.0V to VCC
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max
TABLE 1. HM-6514/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
(NOTE 1)
CONDITIONS
VCC = 4.5V
IOL = 3.2mA
VCC = 4.5V
IOH = -1.0mA
VCC = 5.5V,
VI = GND or VCC
VCC = 5.5 V,
VIO = GND or VCC
VCC = 2.0V,
E = VCC -0.3V,
IO = 0mA
VCC = 5.5V, (Note 2)
E = 1MHz
VCC = 5.5V,
E = VCC-0.3V,
IO = 0mA
GROUP A
SUBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
LIMITS
TEMPERATURE
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
MIN
-
2.4
-1.0
-1.0
-
MAX
0.4
-
+1.0
+1.0
25
UNITS
V
V
A
A
A
PARAMETER
Output Low Voltage
Output High Voltage
Input Leakage Current
Input/Output Leakage
Current
Data Retention Supply
Current
Operating Supply
Current
Standby Supply
Current
NOTES:
SYMBOL
VOL
VOH
II
IIOZ
ICCDR
ICCOP
ICCSB
1, 2, 3
1, 2, 3
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-
-
7
50
mA
A
1. All voltages referenced to device GND.
2. Typical derating 1.5mA/MHz increase in ICCOP.
FN2996 Rev.1.00
March 1997
Page 3 of 9
HM-6514/883
TABLE 2. HM-6514/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
LIMITS
(NOTES 1, 2)
CONDITIONS
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V, Note 3
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
GROUP
A SUB-
GROUPS
9, 10, 11
9, 10, 11
9, 10, 11
TEMPERA-
TURE
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
HM-6514S/883
MIN
-
-
120
MAX
120
120
-
HM-6514B/883
MIN
-
-
200
MAX
200
220
-
HM-6514/883
MIN
-
-
300
MAX
300
320
-
UNITS
ns
ns
ns
PARAMETER
Chip Enable
Access Time
Address Access
Time
Chip Enable
Pulse Negative
Width
Chip Enable
Pulse Positive
Width
Address Setup
Time
Address Hold
Time
Write Enable
Pulse Width
Write Enable
Pulse Setup
Time
Write Enable
Pulse Hold Time
Data Setup Time
Data Hold Time
Write Data Delay
Time
Early Output
High-Z Time
Late Output
High-Z Time
Read or Write
Cycle Time
SYMBOL
(1)
TELQV
(2)
TAVQV
(5)
TELEH
(6)
TEHEL
9, 10, 11
50
-
90
-
120
-
ns
(7)
TAVEL
(8)
TELAX
(9)
TWLWH
(10)
TWLEH
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
0
40
120
120
-
-
-
-
20
50
200
200
-
-
-
-
20
50
300
300
-
-
-
-
ns
ns
ns
ns
(11)
TELWH
(12)
TDVWH
(13)
TWHDX
(14)
TWLDV
(15)
TWLEL
(16)
TEHWH
(17)
TELEL
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
120
50
0
70
0
0
170
-
-
-
-
-
-
-
200
120
0
80
0
0
290
-
-
-
-
-
-
-
300
200
0
100
0
0
420
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. All voltages referenced to device GND.
2. Input pulse levels: 0.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
3. TAVQV = TELQV + TAVEL.
FN2996 Rev.1.00
March 1997
Page 4 of 9
HM-6514/883
TABLE 3. HM-6514/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
HM-6514/883
LIMITS
PARAMETER
Input Capacitance
SYMBOL
CI
CONDITIONS
VCC = Open, f = 1MHz, All
Measurements Referenced
to Device Ground
VCC = Open, f = 1MHz, All
Measurements Referenced
to Device Ground
VCC = 4.5 and 5.5V
VCC = 4.5 and 5.5V
HM-6514S/883
VCC = 4.5 and 5.5V
HM-6514B/883
VCC = 4.5 and 5.5V
HM-6514/883
NOTE
1
TEMPERATURE
T
A
= +25
o
C
MIN
-
MAX
8
UNITS
pF
Input/Output
Capacitance
Chip Enable Output
Disable Time
Chip Enable Output
Disable Time
CIO
1
T
A
= +25
o
C
-
10
pF
TELQX
TEHQZ
1
1
1
1
1
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
-55
o
C
T
A
+125
o
C
5
-
-
-
-
50
80
100
ns
ns
ns
High Level Output
Voltage
NOTES:
VOH2
VCC = 4.5V, IO = -100A
VCC -0.4
-
V
1. The parameters listed in Table 3 are controlled via design, or process parameters are characterized upon initial design and after major
process and/or design changes.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test
Interim Test
PDA
Final Test
Group A
Groups C & D
METHOD
100%/5004
100%/5004
100%/5004
100%/5004
Samples/5005
Samples/5005
SUBGROUPS
-
1, 7, 9
1
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
FN2996 Rev.1.00
March 1997
Page 5 of 9
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