TM
HM-65162
2K x 8 Asynchronous
CMOS Static RAM
Description
The HM-65162 is a CMOS 2048 x 8 Static Random Access
Memory manufactured using the Intersil Advanced SAJI V
process. The device utilizes asynchronous circuit design for
fast cycle time and ease of use. The pinout is the JEDEC 24
pin DIP, and 32 pad 8-bit wide standard which allows easy
memory board layouts flexible to accommodate a variety of
industry standard PROMs, RAMs, ROMs and EPROMs. The
HM-65162 is ideally suited for use in microprocessor based
systems with its 8-bit word length organization. The conve-
nient output enable also simplifies the bus interface by allow-
ing the data outputs to be controlled independent of the chip
enable. Gated inputs lower operating current and also elimi-
nate the need for pull-up or pull-down resistors.
March 1997
Features
• Fast Access Time . . . . . . . . . . . . . . . . . . . 70/90ns Max
• Low Standby Current. . . . . . . . . . . . . . . . . . . . 50µA Max
• Low Operating Current . . . . . . . . . . . . . . . . . 70mA Max
• Data Retention at 2.0V . . . . . . . . . . . . . . . . . . . 20µA Max
• TTL Compatible Inputs and Outputs
• JEDEC Approved Pinout (2716, 6116 Type)
• No Clocks or Strobes Required
• Equal Cycle and Access Time
• Single 5V Supply
• Gated Inputs
• No Pull-Up or Pull-Down Resistors Required
Ordering Information
PACKAGE
CERDIP
JAN#
SMD#
CLCC
SMD#
NOTE:
1. Access time/data retention supply current.
TEMP. RANGE
-40
o
C to +85
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-40
o
C to +85
o
C
-55
o
C to 125
o
C
70ns/20µA
(NOTE 1)
HM1-65162B-9
29110BJA
8403606JA
HM4-65162B-9
8403606ZA
90ns/40µA
(NOTE 1)
HM1-65162-9
29104BJA
8403602JA
HM4-65162-9
8403602ZA
8403603JA
HM4-65162C-9
8403603ZA
90ns/300µA
(NOTE 1)
HM1-65162C-9
-
PKG. NO.
F24.6
F24.6
F24.6
J32.A
J32.A
Pinouts
HM-65162
(CERDIP)
TOP VIEW
NC
A7
HM-65162
(CLCC)
TOP VIEW
V
CC
PIN
NC
NC
30
29 A8
28 A9
27 NC
26 W
25 G
24 A10
23 E
22 DQ7
21 DQ6
DESCRIPTION
No Connect
Address Input
Chip Enable/Power Down
Ground
Data In/Data Out
Power (+5V)
Write Enable
Output Enable
NC
NC
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
1
2
3
4
5
6
7
8
9
24 V
CC
23 A8
22 A9
21 W
20 G
19 A10
18 E
17 DQ7
16 DQ6
15 DQ5
14 DQ4
13 DQ3
A6
A5
A4
A3
A2
5
6
7
8
9
4
3
2
1
32 31
NC
A0 - A10
E
V
SS
/GND
DQ0 - DQ7
V
CC
W
G
A1 10
A0 11
NC 12
DQ0
13
14 15 16
DQ1
DQ2
GND
17
NC
18
DQ3
19
DQ4
20
DQ5
DQ1 10
DQ2 11
GND 12
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
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Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN3000.1
1
HM-65162
Functional Diagram
A1
A
A2
A3
A4
A5
A6
A7
ROW
ADDRESS
BUFFER
7
ROW
DECODER
A
7
128
COLUMN DECODER
AND DATA
INPUT / OUTPUT (X8)
4
A
G
4
A
1 OF 8
DQ0
THRU
DQ7
128
128 X 128
MEMORY ARRAY
8
E
COLUMN
ADDRESS BUFFER
W
A0
A8 A9 A10
2
HM-65162
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to V
CC
+0.3V
Typical Derating Factor . . . . . . . . . . 05mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
CERDIP Package . . . . . . . . . . . . . . . .
48
8
CLCC Package . . . . . . . . . . . . . . . . . .
66
12
Maximum Storage Temperature Range . . . . . . . . .-65
o
C to +150
o
C
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300
o
C
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
HM-65162S-9, HM-65162B-9,
HM-65162-9, HM65162C-9. . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26000 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
V
CC
= 5V
±10%;
T
A
= -40
o
C to +85
o
C (HM-65162S-9, HM-65162B-9, HM-65162-9, HM-65162C-9)
LIMITS
SYMBOL
ICCSB1
PARAMETER
Standby Supply Current
MIN
-
-
MAX
50
100
UNITS
µA
µA
TEST CONDITIONS
HM-65162B-9, IO = 0mA,
E = V
CC
- 0.3V, V
CC
= 5.5V
HM-65162S-9, HM65162-9,
IO = 0mA, E = V
CC
- 0.3V,
V
CC
= 5.5V
HM-65162C-9, IO = 0mA,
E = V
CC
- 0.3V, V
CC
= 5.5V
E = 2.2V, IO = 0mA, V
CC
= 5.5V
E = 0.8V, IO = 0mA, V
CC
= 5.5V
E = 0.8V, IO = 0mA, f = 1MHz,
V
CC
= 5.5V
HM-65162B-9, IO = 0mA,
V
CC
= 2.0V, E = VCC - 0.3V
HM-65162S-9, HM-65162-9,
IO = 0mA, V
CC
= 2.0V,
E = V
CC
- 0.3V
HM-65162C-9, IO = 0mA,
V
CC
= 2.0V, E = V
CC
- 0.3V
VI = V
CC
or GND, V
CC
= 5.5V
VIO = V
CC
or GND, V
CC
= 5.5V
V
CC
= 4.5V
V
CC
= 5.5V
IO = 4.0mA, V
CC
= 4.5V
IO = -1.0mA, V
CC
= 4.5V
IO = -100µA, V
CC
= 4.5V
-
ICCSB
ICCEN
ICCOP
ICCDR
Standby Supply Current
Enabled Supply Current
Operating Supply Current (Note 1)
Data Retention Supply Current
-
-
-
-
-
900
8
70
70
20
40
µA
mA
mA
mA
µA
µA
-
VCCDR
II
IIOZ
V
IL
V
IH
VOL
VOH1
VOH2
Data Retention Supply Voltage
Input Leakage Current
Input/Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage (Note 2)
2.0
-1.0
-1.0
-0.3
2.2
-
2.4
V
CC
-0.4
300
-
+1.0
+1.0
0.8
V
CC
+0.3
0.4
-
-
µA
V
µA
µA
V
V
V
V
V
Capacitance
T
A
= +25
o
C
SYMBOL
CI
CIO
NOTES:
1. Typical derating 5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.
PARAMETER
Input Capacitance (Note 2)
Input/Output Capacitance (Note 2)
MAX
10
12
UNITS
pF
pF
TEST CONDITIONS
f = 1MHz, All measurements are
referenced to device GND
3
HM-65162
AC Electrical Specifications
V
CC
= 5V
±10%,
T
A
= -40
o
C to +85
o
C (HM-65162S-9, HM-65162B-9, HM65162-9, HM-65162C-9)
LIMITS
HM-65162S-9
SYMBOL
READ CYCLE
(1) TAVAX
(2) TAVQV
(3) TELQV
(4) TELQX
(5) TGLQV
(6) TGLQX
(7) TEHQZ
(8) TGHQZ
(9) TAVQX
WRITE CYCLE
(10) TAVAX
(11) TELWH
(12) TAVWL
(13) TWLWH
(14) TWHAX
(15) TGHQZ
(16) TWLQZ
(17) TDVWH
(18) TWHDX
(19) TWHQX
(20) TWLEH
(21) TDVEH
(22) TAVWH
Write Cycle Time
Chip Selection to End of
Write
Address Setup Time
Write Enable Pulse
Width
Write Enable Read
Setup Time
Output Enable Output
Disable Time
Write Enable Output
Disable Time
Data Setup Time
Data Hold Time
Write Enable Output
Enable Time
Write Enable Pulse
Setup Time
Chip Enable Data
Setup Time
Address Valid to End of
Write
55
45
5
40
10
-
-
25
10
0
45
25
45
-
-
-
-
-
30
30
-
-
-
-
-
-
70
45
10
40
10
-
-
30
10
0
40
30
50
-
-
-
-
-
35
40
-
-
-
-
-
-
90
55
10
55
10
-
-
30
15
0
55
30
65
-
-
-
-
-
40
50
-
-
-
-
-
-
90
55
10
55
10
-
-
30
15
0
55
30
65
-
-
-
-
-
40
50
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address Access Time
Chip Enable Access
Time
Chip Enable Output
Enable Time
Output Enable Access
Time
Output Enable Output
Enable Time
Chip Enable Output
Disable Time
Output Enable Output
Disable Time
Output Hold From
Address Change
55
-
-
5
-
5
-
-
5
-
55
55
-
35
-
35
30
-
70
-
-
5
-
5
-
-
5
-
70
70
-
50
-
35
35
-
90
-
-
5
-
5
-
-
5
-
90
90
-
65
-
50
40
-
90
-
-
5
-
5
-
-
5
-
90
90
-
65
-
50
40
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
PARAMETER
MIN
MAX
HM-65162B-9
MIN
MAX
HM-65162-9
MIN
MAX
HM-65162C-9
MIN
MAX
UNITS
CONDITIONS
(Notes 1, 3)
(Notes 1, 3, 4)
(Notes 1, 3)
(Notes 2, 3)
(Notes 1, 3)
(Notes 2, 3)
(Notes 2, 3)
(Notes 2, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 2, 3)
(Notes 2, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
NOTES:
1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent and C
L
= 50pF (min) - for C
L
greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. V
CC
= 4.5 and 5.5V.
4. TAVQV = TELQV + TAVEL.
4
HM-65162
Timing Waveforms
(1) TAVAX
(2) TAVQV
ADDRESS
(8) TGHQZ
G
(5) TGLQV
E
(6) TGLQX
(3) TELQV
Q
(4) TELQX
(9) TAVQX
(7) TEHQZ
NOTE:
1. W is high for a Read Cycle.
FIGURE 1. READ CYCLE
Addresses must remain stable for the duration of the read
cycle. To read, G and E must be
≤
V
IL
and W
≥
V
IH
. The
output buffers can be controlled independently by G while E
is low. To execute consecutive read cycles, E may be tied
low continuously until all desired locations are accessed.
(10) TAVAX
ADDRESS
(11) TELWH
E
(12) TAVWL
W
(16) TWLQZ
Q
(21)
TDVEH
D
(13) TWLWH
(20) TWLEH
(19) TWHQX
(14) TWHAX
(17) TDVWH
(22) TAVWH
(18) TWHDX
NOTE:
1. G is low throughout Write Cycle.
FIGURE 2. WRITE CYCLE I
To write, addresses must be stable, E low and W falling low
for a period no shorter than TWLWH. Data in is referenced
with the rising edge of W, (TDVWH and TWHDX). While
addresses are changing, W must be high. When W falls low,
the I/O pins are still in the output state for a period of TWLQZ
and input data of the opposite phase to the outputs must not
be applied, (Bus contention). If E transitions low
simultaneously with the W line transitioning low, or after the
W transition, the output will remain in a high impedance
state. G is held continuously low.
5
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