DATA SHEET
DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µ
PC8104GR
UP CONVERTER + QUADRATURE MODULATOR IC
FOR DIGITAL MOBILE COMMUNICATION SYSTEMS
DESCRIPTION
The
µ
PC8104GR is a silicon monolithic integrated circuit designed as quadrature modulator for digital mobile
communication systems. This modulator consists of 1.9 GHz up-converter and 400 MHz quadrature modulator which
are packaged in 20 pin SSOP. The device has power save function and can operate 2.7 to 5.5 V supply voltage,
therefore, it can contribute to make RF block small, high performance and low power consumption.
FEATURES
•
•
•
•
20 pin SSOP suitable for high density surface mounting.
High linearity up converter is incorporated; P
RFout(sat)
=
−6
dBm TYP.
Low phase difference due to digital phase shifter is adopted.
Wide operating frequency range.
Up converter; f
RFout
= 800 MHz to 1.9 GHz
Modulator
; f
MODout
= 100 MHz to 400 MHz, f
I/Q
= DC to 10 MHz
•
•
•
External IF filter can be applied between modulator output and up converter input terminal.
Supply voltage: V
CC
= 2.7 to 5.5 V
Equipped with power save function.
APPLICATION
•
•
Digital cordless phones
Digital cellular phones
ORDERING INFORMATION
PART NUMBER
PACKAGE
20 pin plastic SSOP
SUPPLYING FORM
Embossed tape 12 mm wide. QTY 2.5 kp/Reel.
Pin 1 indicates pull-out direction of tape.
µ
PC8104GR-E1
* For evaluation sample order, please contact your local NEC sales office. (Order number:
µ
PC8104GR)
Caution electro-static sensitive device
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. P10099EJ4V0DS00 (4th edition)
Date Published October 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1995, 1999
µ
PC8104GR
INTERNAL BLOCK DIAGRAM AND PIN CONNECTIONS (Top View)
Lo1 in 1
Lo1 in 2
GND 3
(MOD)
I 4
I 5
Q 6
Q 7
GND 8
(UP Con)
RF out 9
GND 10
(UP Con)
90˚
Phase
Shifter
REG.
20 V
CC
19 Power Save
18 GND
17 GND
16 MOD out
15 Up Con in
14 Up Con in
13 V
CC
(UP Con)
12 Lo2 in
11 Lo2 in
APPLICATION EXAMPLE
(PHS)
RX
DEMO.
I
Q
SW
÷N
PLL
PLL
µ
PC8104GR
I
0˚
TX
PA
φ
90˚
Q
Filter
2
Data Sheet P10099EJ4V0DS00
µ
PC8104GR
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage
Power Save Voltage
Power Dissipation
Operating Temperature
Storage Temperature
SYMBOL
V
CC
V
PS
P
D
T
A
T
stg
RATING
6.0
6.0
430
−40
to +85
−55
to +150
UNIT
V
V
mW
°C
°C
TEST CONDITION
T
A
= +25
°C
T
A
= +25
°C
T
A
= +85
°C
Note1
Note 1:
Mounted on 50
×
50
×
1.6 mm double copper clad epoxy glass board
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Operating Temperature
Up Converter RF Frequency
Up Converter Input Freq.
Modulator Output Frequency
Lo1 Input Frequency
Lo2 Input Frequency
I/Q Input Frequency
SYMBOL
V
CC
T
A
f
RFout
f
UpConin
f
MODout
f
Lo1in
f
Lo2in
f
I/Qin
800
DC
1800
10
MHz
MHz
P
Lo1in
=
−10
dBm
P
Lo2in
=
−10
dBm
P
I/Qin
= 600 mV
p-p
MAX (Single ended)
MIN.
2.7
−40
0.8
100
TYP.
3.0
+25
MAX.
5.5
+85
1.9
400
UNIT
V
°C
GHz
MHz
TEST CONDITIONS
ELECTRICAL CHARACTERISTICS (T
A
= +25
°
C, V
CC
= 3.0 V, Unless Otherwise Specified V
PS
≥
1.8 V)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
UP CONVERTER + QUADRATURE MODULATOR TOTAL
Total Circuit Current
Total Circuit Current at
Power-Save Mode
Total Output Power
Lo Carrier Leak
Note2
I
ccTOTAL
I
cc(PS)TOTAL
18
28
0.1
37
10
−8.5
−30
−30
mA
No input signal
V
PS
≤
1.0 V
I/Q DC = 1.5 V
P
I/Qin
= 500 mV
p-p
(Single ended)
µ
A
dBm
dBc
dBc
P
RFout
LOL
ImR
−18.5
−13.5
−40
−40
Image Rejection (Side Band
Leak)
Note 2:
Lo1 + Lo2
Data Sheet P10099EJ4V0DS00
3
µ
PC8104GR
STANDARD CHARACTERISTICS FOR REFERENCE
(T
A
= +25
°
C, V
CC
= 3.0 V, Unless Otherwise Specified V
PS
≥
1.8 V)
PARAMETER
UP CONVERTER BLOCK
Up Con. Circuit Current
Up Con. Circuit Current at
Power-Save Mode
Conversion Gain
Maximum Output Power
Output Intercept Point
I
ccUpCon
I
cc(PS)UpCon
12
5
mA
No input signal
V
PS
≤
1.0 V
SYMBOL
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
µ
A
dB
dBm
dBm
CG
P
RF(sat)
OIP3
4
−6
0
f
RFout
= 1.9 GHz
f
UpConin
= 240.0 MHz/240.2 MHz
QUADRATURE MODULATOR BLOCK
MOD. Circuit Current
MOD. Circuit Current at
Power-Save Mode
Output Power
Lo1 Carrier Leak
Image Rejection
(Side Band Leak)
I/Q 3rd Order Intermodulation
Distortion
I/Q Input Impedance
I/Q Bias Current
Lo1 Input VSWR
Power Save Rise Time
Power Save Fall Time
I
ccMOD
I
cc(PS)MOD
−16.5
−40
−40
−50
−30
−30
−30
10
16
21
5
mA
No input signal
V
PS
≤
1.0 V
µ
A
dBm
dBc
dBc
P
MODout
LOL
ImR
I/Q DC = 1.5 V
P
I/Qin
= 500 mV
p-p
(Single ended)
I
M3I/Q
dBc
I/Q DC = 1.5 V
P
I/Qin
= 500 mV
p-p
(Single ended)
(I
→
I, Q
→
Q)
Z
I/Q
I
I/Q
Z
Lo1
T
PS(RISE)
T
PS(FALL)
20
5
1.2:1
2.0
2.0
5.0
5.0
kΩ
µ
A
X:1
µ
s
µ
s
V
PS(OFF)
→
V
PS(ON)
V
PS(ON)
→
V
PS(OFF)
4
Data Sheet P10099EJ4V0DS00
µ
PC8104GR
PIN EXPLANATION
PIN
NO.
1
ASSIGN-
MENT
Lo1in
SUPPLY
VOL. (V)
−
PIN
VOL.(V)
0
FUNCTION AND APPLICATION
Lo1 input for phase shifter.
This input impedance is 50
Ω
matched internally.
Bypass of Lo1 input.
This pin is grounded through
internal capacitor.
Open in case of single ended.
Connect to the ground with
minimum inductance.
Track length should be kept as
short as possible.
Input for I signal. This input
impedance is larger than 20 kΩ.
Relations between amplitude
and V
CC
/2 bias of input signal
are following.
V
CC
/2 (v)
≥
1.35
≥
1.5
≥
1.75
Amp. (mV
p-p
)
Note
400
600
1000
EQUIPMENT CIRCUIT
1
50
Ω
2
Lo1in
−
2.4
2
3
GND for
modulator
0
−
4
I
V
CC
/2
−
4
5
5
I
V
CC
/2
−
Input for I signal. This input
impedance is larger than 20 kΩ.
V
CC
/2 biased DC signal should
be input.
Input for Q signal. This input
impedance is larger than 20 kΩ.
V
CC
/2 biased DC signal should
be input.
Input for Q signal. This input
impedance is larger than 20 kΩ.
Relations between amplitude
and V
CC
/2 bias of input signal
are following.
V
CC
/2 (v)
≥
1.35
≥
1.5
≥
1.75
Amp. (mV
p-p
)
Note
400
600
1000
6
Q
V
CC
/2
−
7
Q
V
CC
/2
−
7
6
16
MODout
−
1.5
Output from modulator.
This is emitter follower output.
16
Note
In case of that I/Q input signals are single ended.
Of course, I/Q signal inputs can be used either single endedly or differentially with proper terminations.
Data Sheet P10099EJ4V0DS00
5
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