PRELIMINARY
CM3212
DDR VDDQ and VTT Termination Voltage Regulator
Features
•
Two linear regulators
-Maximum 2A current from VDDQ
-Source and sink up to 2A VTT current
1.7V to 2.8V adjustable VDDQ output voltage
0.85V to 1.4V VTT output voltage (tracking at 50% of
VDDQ)
Buffered VREF output
500mV typical VDDQ dropout voltage at 2A
Excellent load and line regulation, low noise
Meets JEDEC DDR-I and DDR-II memory power spec
Linear regulator design requires no inductors and has
low external component count
Integrated power MOSFETs
Dual purpose ADJ/Shutdown pin
Enable VTT pin for sleep or suspend to RAM function
Built-in over-current limit and thermal shutdown for
VDDQ and VTT
Fast transient response
Low quiescent current
TDFN-8 RoHS compliant lead-free package
SOIC-8 RoHS compliant lead-free package
Product Description
T
he CM3212 is a dual-output low noise linear regulator
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•
•
•
•
•
•
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designed to meet SSTL-2 and SSTL-3 specifications
for DDR-SDRAM V
DDQ
supply and termination voltage
V
TT
supply. With integrated power MOSFETs the
CM3212 can source up to 2A of VDDQ continuous
current, and source or sink up to 2A VTT continuous
current. The typical dropout voltage for VDDQ is
500mV at 2A load current.
The CM3212 provides excellent full load regulation and
fast response to transient load changes. It also has
built-in over-current limits and thermal shutdown at
170°C.
The CM3212 supports Suspend-To-RAM (STR) and
ACPI compliance with Shutdown Mode which tri-states
VTT to minimize quiescent system current.
The CM3212 is available in a space saving TDFN-8
and SOIC-8 surface mount packages. Low thermal
resistance allows them to withstand high power
dissipation at 85°C ambient. The CM3212 can operate
over the industrial ambient temperature range of –40°C
to 85°C.
Applications
•
•
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DDR memory and active termination buses
Desktop computers, servers
Residential and enterprise gateways
DSL modems
Routers and switches
DVD recorders, LCD TV and STB
3D AGP cards
Typical Application
V
IN
= 3.0V to 3.6V
C
IN
4.7μ/10V
cer
1
2
3
4
220μ/10V
V
DDQ
= 2.5V/2A
VDDQ
C
DDQ
4.7μ
10V
cer
VDDQ
220μ
10V
VIN
VTT
NC
GND
VDDQ
EN_VTT
8
7
6
5
S/D
R2
10k
R1
10k
C hip
S et
DL0
RT0
DLn
RTn
CM3212
ADJSD
VREF
REF
Memory
DDR
V
TT
= 1.25V/2A
C
TT
4.7μ
10V
cer
220μ/10V
C
REF
0.1μF/10V
© 2006 California Micro Devices Corp. All rights reserved.
01/04/07
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
1
PRELIMINARY
CM3212
Package Pinout
PACKAGE / PINOUT DIAGRAM
Top View
(Pins Down View)
Pin 1
Marking
Top View
Thermal Pad
VIN
VTT
NC
GND
(Pins Down View)
VIN
VTT
NC
GND
1
8
VDDQ
EN_VTT
ADJSD
VREF
1
8
VDDQ
EN_VTT
ADJSD
VREF
CM3212
02SM
CM321
202DE
2
3
4
7
6
5
2
3
4
7
6
5
8-Lead TDFN Package
CM3212-02DE
Note: These drawings are not to scale.
8-Lead SOIC Package
CM3212-02SM
PIN DESCRIPTIONS
PIN(s)
TDFN-8
1
2
3
4
5
PIN(s)
SOIC-8
1
2
3
4
5
NAME
VIN
VTT
NC
GND
VREF
DESCRIPTION
Input supply voltage pin. Bypass with a 220μF capacitor to GND.
V
TT
regulator output pin, which is preset to 50% of V
DDQ
.
Not internally connected. For better heat flow, connect to GND (exposed pad).
Ground pin.
Reference voltage output pin. This pin buffers internal reference of V
DDQ
/2. Bypass
with 0.1μF ceramic to GND. It is available as long as V
DDQ
is enabled. During
Manual Shutdown or Thermal Shutdown, it is tied to GND.
This pin is for V
DDQ
output voltage adjustment. It is available as long as V
DDQ
is
enabled. During Manual/Thermal shutdown, it is tightened to GND. The V
DDQ
output
voltage is set using an external resistor divider connected to ADJSD:
R1 + R2
-
V
DDQ
= 1.25V
×
--------------------
R2
where R1 is the upper resistor and R2 is the ground-side resistor. In addition, the
ADJSD pin functions as a Shutdown pin. When ADJSD voltage is higher than 2.7V
(SHDN_H), the circuit is in Shutdown mode. When ADJSD voltage is below 1.5V
(SHDN_L), both VDDQ and VTT are enabled. A low-leakage Schottky diode in series
with ADJSD pin is recommended to avoid interference with the voltage adjustment
setting.
7
8
EPad
7
8
EN_VTT
VDDQ
GND
Enable pin for V
TT
regulator (it is internally pulled ‘high’). A logic HIGH on this pin
enables the V
TT
output, and a logic LOW on this pin tri-states the V
TT
output.
VDDQ regulator output voltage pin.
The backside exposed pad which serves as the package heatsink. Must be
connected to GND.
6
6
ADJSD
© 2006 California Micro Devices Corp. All rights reserved.
2
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
01/04/07
PRELIMINARY
CM3212
Ordering Information
PART NUMBERING INFORMATION
Lead-free Finish
Pins
8
8
Package
TDFN
SOIC
Ordering Part Number
1
CM3212-02DE
CM3212-02SM
Part Marking
CM321 202DE
CM3212 02SM
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VIN to GND
Pin Voltages
V
DDQ
,V
TT
to GND
ADJSD to GND
Output Current
VDDQ / VTT, continuous
(1)
VDDQ / VTT, peak
VDDQ Source + VTT Source
Temperature
Operating Ambient
Operating Junction
Storage
Thermal Resistance, R
JA(2)
TDFN-8, 3mm x 3mm
SOIC-8
Continuous Power Dissipation
(2)
TDFN-8, T
A
= 25°C / 85°C
SOIC-8, T
A
= 25°C / 85°C
ESD Protection (HBM)
Lead Temperature (soldering, 10sec)
RATING
[GND - 0.3] to +6.0
[GND - 0.3] to +6.0
[GND - 0.3] to +6.0
2.0 / ± 2.0
2.8 / ± 2.8
3
–40 to +85
–40 to + 170
–40 to +150
55
120
2.6 / 1.5
1.2 / 0.7
2000
300
UNITS
V
V
V
A
A
A
°C
°C
°C
°C/W
°C/W
W
W
V
°C
Note 1: Despite the fact that the device is designed to handle large continuous/peak output currents, it is not capable of handling
these under all conditions. Limited by the package thermal resistance, the maximum output current of the device cannot
exceed the limit imposed by the maximum power dissipation value.
Note 2: Measured with the package using a 4 in
2
/ 2 layers PCB with thermal vias.
© 2006 California Micro Devices Corp. All rights reserved.
01/04/07
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
3
PRELIMINARY
CM3212
Specifications (cont’d)
STANDARD OPERATING CONDITIONS
PARAMETER
Ambient Operating Temperature Range
VDDQ Regulator
Supply Voltage, VIN
Load Current, Continuous
Load Current, Peak (1 sec)
C
DDQ
VTT Regulator
Supply Voltage, VIN
Load Current, Continuous
Load Current, Peak (1 sec)
C
TT
VIN Supply Voltage Range
VDDQ Source + VTT Source
Load Current, Continuous
Load Current, Peak (1 sec)
Junction Operating Temperature Range
RATING
–40 to +85
3.0 to 3.6
0 to 2
2.5
220
3.0 to 3.6
0 to
±2.0
±2.50
220
3.0 to 3.6
2.5
3.5
–40 to +150
UNITS
°C
V
A
A
μF
V
A
A
μF
V
A
A
°C
ELECTRICAL OPERATING CHARACTERISTICS
(SEE NOTE 1)
SYMBOL
General
VIN
I
Q
V
ADJSD
I
SHDN
SHDN_H
SHDN_L
UVLO
T
OVER
T
HYS
TEMPCO
PARAMETER
Supply Voltage Range
Quiescent Current
ADJSD Voltage
Shutdown Current
ADJSD Logic High
ADJSD Logic Low
Under-voltage Lockout
Thermal SHDN Threshold
Thermal SHDN Hysteresis
V
DDQ
, V
TT
TEMPCO
CONDITIONS
MIN
3.0
I
DDQ
= 0, I
TT
= 0
(3)
TYP
MAX
3.6
15
1.275
0.5
1.5
2.90
UNITS
V
mA
V
mA
V
V
V
°C
°C
ppm/°C
1.225
2.7
2.40
150
V
ADJSD
= 3.3V (shutdown)
(2)
(3)
7
1.250
0.2
Hysteresis = 100mV
(3)
(3)
2.70
170
50
100
2.500
10
5
500
I
OUT
= 1A
(3)
I
DDQ
= 100mA
10mA
≤
I
DDQ
≤
2A
(4)
3.0V
≤
VIN
≤
3.6V, I
DDQ
= 0.1A
I
DDQ
= 2A
(5)
(3)
VDDQ Regulator
VDDQ Output Voltage
V
DDQ DEF
VDDQ Load Regulation
V
DDQ LOAD
V
DDQ LINE
V
DROP
I
ADJ
I
DDQ LIM
VTT Regulator
V
TT DEF
VDDQ Line Regulation
VDDQ Dropout Voltage
ADJSD Bias Current
VDDQ Current Limit
VTT Output Voltage
2.450
2.550
25
25
3
V
mV
mV
mV
μA
A
V
2.0
I
TT
= 100mA
1.225
0.8
2.5
1.250
1.275
© 2006 California Micro Devices Corp. All rights reserved.
4
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
01/04/07
PRELIMINARY
CM3212
Specifications (cont’d)
ELECTRICAL OPERATING CHARACTERISTICS
(SEE NOTE 1)
SYMBOL
V
TT LOAD
V
TT LINE
I
TT LIM
I
VTT OFF
V
REF
PARAMETER
VTT Load Regulation
CONDITIONS
Source, 10mA
≤
I
TT
≤
2A
(4)
–30
Sink, -2A
≤
I
TT
≤
10mA
(4)
3.0V
≤
VIN
≤
3.6V, I
TT
= 0.1A
Source / Sink
(4)
V
EN_VTT
= 0.4V (shutdown)
C
REF
= 0.1μF, I
REF
= 100μA
MIN
TYP
10
–10
5
±2.5
1.250
MAX
30
UNITS
mV
mV
mV
A
μA
V
VTT Line Regulation
ITT Current Limit
VTT Shutdown Leakage Current
Reference Voltage
15
10
1.275
±2.0
1.225
Note 1: VIN = 3.3V, V
DDQ
= 2.50V, VTT = 1.25V (default values), C
DDQ
=C
TT
=47μF, T
A
= 25°C unless otherwise specified.
Note 2: The ADJSD Logic High value is normally satisfied for full input voltage range by using a low leakage current (below 1
μ
A).
Schottky diode at ADJSD control pin.
Note 3: Guaranteed by design.
Note 4: Load and line regulation are measured at constant junction temperature by using pulse testing with a low duty cycle. For
high current tests, correlation method can be used. Changes in output voltage due to heating effects must be taken into
account separately. Load and line regulation values are guaranteed up to the maximum power dissipation.
Note 5: Dropout voltage is the input to output voltage differential at which output voltage has dropped 100mV from the nominal value
obtained at 3.3V input. It depends on load current and junction temperature. Guaranteed by design.
Functional Block Diagram
Vref1
Current
Limit
Vref
Current
Limit
Current
Limit
CM3212
© 2006 California Micro Devices Corp. All rights reserved.
01/04/07
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
5
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