Revision-A0.2E
29.Jan.'99
MITSUBISHI LSIs
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5V208A is a family of low voltage 2-Mbit static RAMs
organized as 262,144-words by 8-bit, fabricated by Mitsubishi's high-
performance 0.25µm CMOS technology.
The M5M5V208A is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectives.
The M5M5V208A is packaged in 32-pin 8mm x 13.4mm STSOP
packages. Two types of STSOPs are available, M5M5V208AKV
(normal-lead-bend STSOP) and M5M5V208AKR (reverse-lead-bend
STSOP). These two types STSOPs are suitable for a surface
mounting on double-sided printed circuit boards.
From the point of operating temperature, the family is divided into
three versions; "Standard", "W-version", and "I-version". Those are
summarized in the part name table below.
FEATURES
• Single 2.7 ~ 3.6V power supply
• No clocks, No refresh
• All inputs and outputs are TTL compatible.
• Easy memory expansion and power down by S1 & S2
• Data retention supply voltage=2.0V
• Three-state outputs: OR-tie capability
• OE prevents data contention in the I/O bus
• Common Data I/O
• Battery backup capability
• Small stand-by current • • • • • • • • • • 0.3µA(typ.)
PACKAGE
M5M5V208AKV,KR : 32pin 8 X 13.4 mm TSOP
Stand-by current
I
cc(PD)
, Vcc=3.0V
typical *
Ratings (max.)
25°C 40°C 25°C 40°C 70°C
---
---
---
---
---
---
---
---
85°C
---
---
Active
current
Icc1
(3.0V, typ.)
PART NAME TABLE
Version,
Operating
temperature
Part name
(## stands for"KV"or"KR")
Power
Supply
Access
time
max.
Standard
0 ~ +70°C
W-version
-20 ~ +85°C
I-version
-40 ~ +85°C
M5M5V208
A
##
-55L
2.7
M5M5V208
A
##
-70L
M5M5V208
A
##
-55H
2.7
M5M5V208
A
##
-70H
M5M5V208
A
##
-55LW
M5M5V208
A
##
-70LW
2.7
M5M5V208
A
##
-55HW
M5M5V208
A
##
-70HW
2.7
M5M5V208
A
##
-55LI
M5M5V208
A
##
-70LI
2.7
M5M5V208
A
##
-55HI
M5M5V208
A
##
-70HI
2.7
55ns
---
~ 3.6V 70ns
~ 3.6V 55ns 0.3µA
70ns
55ns
---
~ 3.6V 70ns
55ns
~ 3.6V 70ns 0.3µA
55ns
---
~ 3.6V 70ns
55ns
~ 3.6V 70ns 0.3µA
20µA
1µA 3µA 8µA
---
---
20mA
(f=10MHz)
20µA 50µA
3mA
(f=1MHz)
1µA 3µA 8µA 24µA
---
---
20µA 50µA
1µA 3µA 8µA 24µA
* "typical" parameter is sampled, not 100% tested.
PIN CONFIGURATION (TOP VIEW)
A
11
A
9
A
8
A
13
W
S
2
A
15
Vcc
A
17
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
M5M5V208AKV
OE
A
10
S
1
DQ8
DQ7
DQ6
DQ5
DQ4
GND
DQ3
DQ2
DQ1
A
0
A
1
A
2
A
3
S
2
W
A
4
A
5
A
6
A
7
A
12
A
14
A
16
A
17
Vcc
A
15
A
13
A
8
A
9
A
11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
M5M5V208AKR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A
3
A
2
A
1
A
0
DQ1
DQ2
DQ3
GND
DQ4
DQ5
DQ6
DQ7
DQ8
S
1
A
10
OE
Outline 32P3K-B(KV)
Outline 32P3K-C(KR)
MITSUBISHI ELECTRIC
1
Revision-A0.2E
29.Jan.'99
MITSUBISHI LSIs
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5V208A is determined by a
combination of the device control inputs S
1
, S
2
, W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W
overlaps with the low level S
1
and the high level S
2
. The
address must be set up before the write cycle and must be
stable during the entire cycle. The data is latched into a cell
on the trailing edge of W, S
1
or S
2
, whichever occurs first,
requiring the set-up and hold time relative to these edge to
be maintained. The output enable OE directly controls the
output stage. Setting the OE at a high level,the output stage
is in a high-impedance state, and the data bus contention
problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and
OE at a low level while S
1
and S
2
are in an active state (S
1
= L ,S
2
= H).
When setting S
1
at a high level or S
2
at a low level, the
chips are in a non-selectable mode in which both reading
and writing are disabled. In this mode, the output stage is in
a high-impedance state, allowing OR-tie with other chips
and memory expansion by S
1
or S
2
. The power supply
current is reduced as low as the stand-by current which is
specified as Icc3 or Icc4, and the memory data can be held
at +2V power supply, enabling battery back-up operation
during power failure or power-down operation in the non-
selected mode.
FUNCTION TABLE
S
1
X
H
L
L
L
S
2
L
X
H
H
H
W
X
X
L
H
H
OE
X
X
X
L
H
Mode
Non selection
Non selection
Write
Read
DQ
High-impedance
High-impedance
D
IN
D
OUT
High-impedance
Icc
Standby
Standby
Active
Active
Active
BLOCK DIAGRAM
*
A
4
A
5
A
6
A
7
A
12
A
14
A
16
A
17
A
15
8
7
6
5
4
3
2
1
31
16
15
14
13
12
11
10
9
7
262144 WORDS
X 8 BITS
512 ROWS
X 128 COLUMNS
X 32 BLOCKS
21
22
23
25
26
27
28
29
13
14
15
17
18
19
20
21
*
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
A
0
A
1
A
2
A
3
A
10
A
11
A
9
A
8
A
13
12
11
10
9
23
25
26
27
28
20
19
18
17
5
31
1
2
3
4
8
32
30
6
32
29
22
30
24
CLOCK
GENERATOR
W
S
1
S
2
OE
V
CC
(3V)
24
16
GND
(0V)
*Pin numbers inside dotted line show reverse-lead-bend sTSOP.
MITSUBISHI ELECTRIC
2
Revision-A0.2E
29.Jan.'99
MITSUBISHI LSIs
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Supply voltage
Vcc
V
I
V
O
Pd
Topr
Tstr
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Conditions
With respect to GND
Ta=25°C
Ratings
- 0.5
*
~4.6
- 0.5
*
~ Vcc + 0.5
(Max 4.6)
Unit
V
V
V
mW
0 ~ Vcc
700
Standard
W - Version
I - Version
* - 3.0V in case of AC ( Pulse width
≤
30ns )
0 ~ 70
- 20 ~ 85
- 40 ~ 85
- 65 ~150
°C
°C
°C
°C
DC ELECTRICAL CHARACTERISTICS
Symbol
V
IH
V
IL
V
OH1
V
OH2
V
OL
I
I
I
O
Icc
1
Parameter
High-level input voltage
Low-level input voltage
High-level output voltage 1
High-level output voltage 2
Low-level output voltage
Input current
Output current in off-state
Active supply current
(CMOS-level Input)
(Vcc= 2.7 ~ 3.6V, unless otherwise noted)
Limits
Test conditions
Min
2.0
I
OH
= - 0.5mA
I
OH
= - 0.05mA
I
OL
=2mA
V
I
=0
~
Vcc
S
1
=V
IH
or S
2
=V
IL
or OE=V
IH
V
I/O
=0 ~ Vcc
Typ
- 0.3*
2.4
Vcc
-0.5V
Max
Vcc
+0.3V
0.6
Unit
V
V
V
V
0.4
±1
±1
f= 10MHz
f= 5MHz
f= 1MHz
f= 10MHz
f= 5MHz
f= 1MHz
V
µA
µA
S
1
≤
0.2V, S
2
≥
Vcc-0.2V
,
o
ther inputs
≤
0.2V
or
≥
Vcc-0.2V,output-open
S
1
=V
IL
,S
2
=V
IH
,
o
ther inputs=V
IH
or V
IL
output-open
1) S
2
≤
0.2V,
other inputs=0 ~ Vcc
or
2) S
1
≥
Vcc-0.2V,
S
2
≥
Vcc-0.2V
other inputs=0 ~ Vcc
Icc
2
Active supply current
(TTL-level Input)
20
10
3
22
12
3
0.3
-L
Icc
3
Stand-by current
~+25°C
~+40°C
~+70°C
-HW / I
~+85°C
-H
-HW
-HI
Icc
4
Stand-by current
S
1
=V
IH
or S
2
=V
IL
,other inputs=0
~
Vcc
25
13
5
27
15
5
60
2
5
10
30
0.33
mA
mA
µA
mA
* - 3.0V in case of AC ( Pulse width
≤
30ns )
CAPACITANCE
Symbol
C
I
C
O
Parameter
Input capacitance
Output capacitance
(Vcc= 2.7 ~ 3.6V, unless otherwise noted)
Test conditions
V
I
=GND, V
I
=25mVrms, f=1MHz
V
O
=GND,V
O
=25mVrms, f=1MHz
Min
Limits
Typ
Max
Unit
pF
pF
8
10
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is for Vcc = 3V, Ta = 25°C
MITSUBISHI ELECTRIC
3
Revision-A0.2E
29.Jan.'99
MITSUBISHI LSIs
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(1) MEASUREMENT CONDITIONS
.................................
Vcc
Input pulse level
.............
Input rise and fall time
.....
Reference level
...............
Output loads
...................
( Vcc= 2.7 ~ 3.6V, unless otherwise noted)
1TTL
DQ
CL
including
scope and JIG
Fig.1 Output load
2.7 ~ 3.6V
V
IH
=2.2V,V
IL
=0.4V
5ns
V
OH
=V
OL
=1.5V
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
(2) READ CYCLE
Limits
Symbol
t
CR
t
a
(A)
t
a
(S
1
)
t
a
(S
2
)
t
a
(OE)
t
dis
(S
1
)
t
dis
(S
2
)
t
dis
(OE)
t
en
(S
1
)
t
en
(S
2
)
t
en
(OE)
t
V
(A)
Parameter
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Output enable access time
Output disable time after S
1
high
Output disable time after S
2
low
Output disable time after OE high
Output enable time after S
1
low
Output enable time after S
2
high
Output enable time after OE low
Data valid time after address
-55L,H
Min
Max
-70L,H
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
55
55
55
30
20
20
20
10
10
5
10
70
70
70
70
35
25
25
25
10
10
5
10
(3) WRITE CYCLE
Limits
Symbol
t
CW
t
w
(W)
t
su
(A)
t
su
(A-WH)
t
su
(S
1
)
t
su
(S
2
)
t
su
(D)
t
h
(D)
t
rec
(W)
t
dis
(W)
t
dis
(OE)
t
en
(W)
t
en
(OE)
Parameter
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to W
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
-55L,H
Min
Max
-55L,H
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
45
0
50
50
50
25
0
0
5
5
20
20
70
55
0
65
65
65
30
0
0
5
5
25
25
MITSUBISHI ELECTRIC
4
Revision-A0.2E
29.Jan.'99
MITSUBISHI LSIs
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
A
0~17
t
a
(A)
t
a
(S1)
S
1
(Note 3)
t
CR
t
v
(A)
t
dis
(S1)
(Note 3)
S
2
(Note 3)
t
a
(S2)
t
a
(OE)
t
en
(OE)
t
dis
(S2)
(Note 3)
OE
(Note 3)
t
dis
(OE)
t
en
(S1)
t
en
(S2)
(Note 3)
DQ
1~8
W = "H" level
DATA VALID
Write cycle (W control mode)
A
0~17
t
CW
t
su
(S1)
S
1
(Note 3)
(Note 3)
S
2
(Note 3)
t
su
(S2)
(Note 3)
t
su
(A-WH)
OE
t
su
(A)
W
t
dis
(W)
t
dis
(OE)
DQ
1~8
t
en
(W)
t
en
(OE)
t
w
(W)
t
rec
(W)
DATA IN
STABLE
t
su
(D)
t
h
(D)
MITSUBISHI ELECTRIC
5
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