Direct RDRAM
™
128/144Mbit (256Kx16/18x32s) Preliminary
Overview
The Rambus Direct RDRAM™ is a general purpose high-
performance memory device suitable for use in a broad
range of applications including computer memory, graphics,
video, and any other application where high bandwidth and
low latency are required.
The 128/144-Mbit Direct Rambus DRAMs (RDRAM®) are
extremely high-speed CMOS DRAMs organized as 8M
words by 16 or 18 bits. The use of Rambus Signaling Level
(RSL) technology permits 600MHz to 800MHz transfer
rates while using conventional system and board design
technologies. Direct RDRAM devices are capable of
sustained data transfers at 1.25 ns per two bytes (10ns per
sixteen bytes).
The architecture of the Direct RDRAMs allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and
data buses with independent row and column control yield
over 95% bus efficiency. The Direct RDRAM's 32 banks
support up to four simultaneous transactions.
System oriented features for mobile, graphics and large
memory systems include power management, byte masking,
and x18 organization. The two data bits in the x18 organiza-
tion are general and can be used for additional storage and
bandwidth or for error correction.
Figure 1: Direct RDRAM uBGA Package
The 128/144-Mbit Direct RDRAMs are offered in a uBGA
package suitable for desktop as well as low-profile add-in
card and mobile applications.
Direct RDRAMs operate from a 2.5 volt supply.
Key Timing Parameters/Part Numbers
Organization
a
256Kx16x32s
256Kx16x32s
256Kx16x32s
256Kx16x32s
256Kx18x32s
256Kx18x32s
256Kx18x32s
256Kx18x32s
256Kx18x32s
256Kx18x32s
256Kx18x32s
256Kx18x32s
I/O Freq. Core Access Time
MHz
(ns)
600
711
800
800
600
711
800
800
600
711
800
800
53
45
45
40
53
45
45
40
53
45
45
40
Part
Number
HY5R128HC653
HY5R128HC745
HY5R128HC845
HY5R128HC840
HY5R144HC653
HY5R144HC745
HY5R144HC845
HY5R144HC840
HY5R144HM
b
653
HY5R144HM745
HY5R144HM845
HY5R144HM840
Features
•
Highest sustained bandwidth per DRAM device
- 1.6GB/s sustained data transfer rate
- Separate control and data buses for maximized
efficiency
- Separate row and column control buses for
easy scheduling and highest performance
- 32 banks: four transactions can take place simul-
taneously at full bandwidth data rates
•
Low latency features
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
•
Advanced power management:
- Multiple low power states allows flexibility in
power consumption versus time to transition to active
state
- Power-down self-refresh
•
Organization: 1Kbyte pages and 32 banks, x 16/18
- x18 organization allows ECC configurations or
increased storage/bandwidth
- x16 organization for low cost applications
•
Uses Rambus Signaling Level (RSL) for up to
800MHz operation
a. The “32s” designation indicates that this RDRAM core is com-
posed of 32 banks which use a “split” bank architecture.
b. The “M” indicates the mirrored package.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1/June.00
1
128/144Mbit (256Kx16/18x32s)
Pinouts and Definitions
Center-Bonded Devices
These tables shows the pin assignments of the center-bonded
RDRAM package. The top table is for the normal package,
and the bottom table is for the mirrored package. The
mechanical dimensions of this package are shown in a later
section. Refer to Section "Center-Bonded uBGA Package"
on page 60. ( Note : pin#1 is at the A1 position. )
Table 1: Center-Bonded Device (top view for Normal Package)
12
11
10
9
8
7
6
5
4
3
2
1
GND
VDD
VDD
GND
SCK
VCMOS
DQA8
DQA6
GND
DQA3
DQA1
VDD
DQA0
VREF
GND
CTMN
RQ7
GND
CTM
RQ1
VDD
RQ4
DQB2
GND
RQ0
DQB6
GND
DQB3
SIO0
VCMOS
DQB8
DQA7
GND
CMD
DQA4
VDD
DQA5
CFM
GND
DQA2
CFMN
GNDa
VDDa
RQ5
VDD
RQ6
RQ3
GND
RQ2
DQB0
VDD
DQB1
DQB4
VDD
DQB5
DQB7
GND
SIO1
GND
VDD
VDD
GND
A
B
C
D
E
F
G
H
J
Table 2: Center-Bonded Device (top view for Mirrored Package)
12
11
10
9
8
7
6
5
4
3
2
1
GND
VDD
VDD
GND
CMD
GND
DQA7
DQA5
VDD
DQA4
DQA2
GND
CFM
VDDa
GNDa
CFMN
RQ6
VDD
RQ5
RQ2
GND
RQ3
DQB1
VDD
DQB0
DQB5
VDD
DQB4
SIO1
GND
DQB7
DQA8
VCMOS
SCK
DQA3
GND
DQA6
DQA0
VDD
DQA1
CTMN
GND
VREF
CTM
GND
RQ7
RQ4
VDD
RQ1
RQ0
GND
DQB2
DQB3
GND
DQB6
DQB8
VCMOS
SIO0
GND
VDD
VDD
GND
A
B
C
D
E
F
G
H
J
2
Rev.1.1 June.00
128/144Mbit (256Kx16/18x32s)
Table 3: Pin Description
Signal
SIO1,SIO0
I/O
I/O
Type
CMOS
a
# Pins
center
2
Description
Serial input/output. Pins for reading from and writing to the control
registers using a serial access protocol. Also used for power manage-
ment.
Command input. Pins used in conjunction with SIO0 and SIO1 for
reading from and writing to the control registers. Also used for power
management.
Serial clock input. Clock source used for reading from and writing to
the control registers
Supply voltage for the RDRAM core and interface logic.
Supply voltage for the RDRAM analog circuitry.
Supply voltage for CMOS input/output pins.
Ground reference for RDRAM core and interface.
Ground reference for RDRAM analog circuitry.
Data byte A. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM. DQA8 is not used by
RDRAMs with a x16 organization.
Clock from master. Interface clock used for receiving RSL signals
from the Channel. Positive polarity.
Clock from master. Interface clock used for receiving RSL signals
from the Channel. Negative polarity
Logic threshold reference voltage for RSL signals
Clock to master. Interface clock used for transmitting RSL signals to
the Channel. Negative polarity.
Clock to master. Interface clock used for transmitting RSL signals to
the Channel. Positive polarity.
Row access control. Three pins containing control and address infor-
mation for row accesses.
Column access control. Five pins containing control and address
information for column accesses.
Data byte B. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM. DQB8 is not used by
RDRAMs with a x16 organization.
CMD
I
CMOS
a
1
SCK
I
CMOS
a
1
V
DD
V
DDa
V
CMOS
GND
GNDa
DQA8..DQA0
I/O
RSL
b
10
1
2
13
1
9
CFM
I
RSL
b
RSL
b
1
CFMN
I
1
V
REF
CTMN
I
RSL
b
RSL
b
RSL
b
RSL
b
RSL
b
1
1
CTM
I
1
RQ7..RQ5 or
ROW2..ROW0
RQ4..RQ0 or
COL4..COL0
DQB8..
DQB0
I
3
I
5
I/O
9
Total pin count per package
62
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
Rev.1.1 June.00
3
128/144Mbit (256Kx16/18x32s)
DQB8..DQB0
9
RQ7..RQ5 or
ROW2..ROW0
3
CTM CTMN SCK,CMD SIO0,SIO1 CFM CFMN
2
2
RCLK
1:8 Demux
TCLK
Packet Decode
ROWR
ROWA
11 5
5
9
ROP DR BR
AV
Match
RQ4..RQ0 or
COL4..COL0
5
DQA8..DQA0
9
RCLK
1:8 Demux
RCLK
Control Registers
6
REFR
Power Modes
COLX
5
5
Packet Decode
COLC
5
5
5
6
C
8
COLM
8
R
DEVID
XOP DX BX COP DC BC
M
S
Match
XOP Decode
Match
MB MA
Mux
Row Decode
DM
Write
Buffer
Mux
Mux
PRER
ACT
Sense Amp
32x72
SAmp SAmp SAmp
PREX
Column Decode & Mask
DRAM Core
32x72 512x64x144
Bank 0
32x72
0
72
SAmp SAmp SAmp
PREC
RD, WR
Internal DQB Data Path
0
72
Internal DQA Data Path
0/1
0/1
72
Bank 1
1/2
1/2
Bank 2
72
RCLK
9
9
•••
9
•••
9
RCLK
SAmp SAmp SAmp
14/15 13/14
Bank 13
Bank 14
Bank 15
•••
13/14 14/15 15
SAmp SAmp SAmp
Write Buffer
1:8 Demux
Write Buffer
1:8 Demux
9
9
SAmp SAmp SAmp
15
SAmp SAmp SAmp
17/18 16/17 16
16
Bank 16
Bank 17
Bank 18
•••
16/17 17/18
TCLK
9
9
TCLK
•••
8:1 Mux
•••
8:1 Mux
9
9
SAmp SAmp SAmp
30/31 29/30
Bank 29
Bank 30
Bank 31
SAmp SAmp SAmp
29/30 30/31 31
Figure 2: 128/144 Mbit Direct RDRAM Block Diagram
4
31
Rev.1.1 June.00
128/144Mbit (256Kx16/18x32s)
General Description
Figure 2 is a block diagram of the 128/144 Mbit Direct
RDRAM. It consists of two major blocks: a “core” block
built from banks and sense amps similar to those found in
other types of DRAM, and a Direct Rambus interface block
which permits an external controller to access this core at up
to 1.6GB/s.
24-bit ROWA (row-activate) or ROWR (row-operation)
packet.
COL Pins:
The principle use of these five pins is to
manage the transfer of data between the DQA/DQB pins and
the sense amps of the RDRAM. These pins are de-multi-
plexed into a 23-bit COLC (column-operation) packet and
either a 17-bit COLM (mask) packet or a 17-bit COLX
(extended-operation) packet.
Control Registers:
The CMD, SCK, SIO0, and SIO1
pins appear in the upper center of Figure 2. They are used to
write and read a block of control registers. These registers
supply the RDRAM configuration information to a
controller and they select the operating modes of the device.
The nine bit REFR value is used for tracking the last
refreshed row. Most importantly, the five bit DEVID speci-
fies the device address of the RDRAM on the Channel.
ACT Command:
An ACT (activate) command from an
ROWA packet causes one of the 512 rows of the selected
bank to be loaded to its associated sense amps (two 256 byte
sense amps for DQA and two for DQB).
PRER Command:
A PRER (precharge) command from
an ROWR packet causes the selected bank to release its two
associated sense amps, permitting a different row in that
bank to be activated, or permitting adjacent banks to be acti-
vated.
Clocking:
The CTM and CTMN pins (Clock-To-Master)
generate TCLK (Transmit Clock), the internal clock used to
transmit read data. The CFM and CFMN pins (Clock-From-
Master) generate RCLK (Receive Clock), the internal clock
signal used to receive write data and to receive the ROW and
COL pins.
RD Command:
The RD (read) command causes one of
the 64 dualocts of one of the sense amps to be transmitted on
the DQA/DQB pins of the Channel.
WR Command:
The WR (write) command causes a
dualoct received from the DQA/DQB data pins of the
Channel to be loaded into the write buffer. There is also
space in the write buffer for the BC bank address and C
column address information. The data in the write buffer is
automatically retired (written with optional bytemask) to one
of the 64 dualocts of one of the sense amps during a subse-
quent COP command. A retire can take place during a RD,
WR, or NOCOP to another device, or during a WR or
NOCOP to the same device. The write buffer will not retire
during a RD to the same device. The write buffer reduces the
delay needed for the internal DQA/DQB data path turn-
around.
DQA,DQB Pins:
These 18 pins carry read (Q) and write
(D) data across the Channel. They are multiplexed/de-multi-
plexed from/to two 72-bit data paths (running at one-eighth
the data frequency) inside the RDRAM.
Banks:
The 16Mbyte core of the RDRAM is divided into
32 x 0.5Mbyte banks, each organized as 512 rows, with each
row containing 64 dualocts, and each dualoct containing 16
bytes. A dualoct is the smallest unit of data that can be
addressed.
Sense Amps:
The RDRAM contains 34 sense amps. Each
sense amp consists of 512 bytes of fast storage (256 for
DQA and 256 for DQB) and can hold one-half of one row of
one bank of the RDRAM. The sense amp may hold any of
the 512 half-rows of an associated bank. However, each
sense amp is shared between two adjacent banks of the
RDRAM (except for sense amps 0, 15, 16, and 31). This
introduces the restriction that adjacent banks may not be
simultaneously accessed.
PREC Precharge:
The PREC, RDA and WRA
commands are similar to NOCOP, RD and WR, except that
a precharge operation is performed at the end of the column
operation. These commands provide a second mechanism
for performing precharge.
PREX Precharge:
After a RD command, or after a WR
command with no byte masking (M=0), a COLX packet may
be used to specify an extended operation (XOP). The most
important XOP command is PREX. This command provides
a third mechanism for performing precharge.
RQ Pins:
These pins carry control and address informa-
tion. They are broken into two groups. RQ7..RQ5 are also
called ROW2..ROW0, and are used primarily for controlling
row accesses. RQ4..RQ0 are also called COL4..COL0, and
are used primarily for controlling column accesses.
ROW Pins:
The principle use of these three pins is to
manage the transfer of data between the banks and the sense
amps of the RDRAM. These pins are de-multiplexed into a
Rev.1.1 June.00
5
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