NCP4303A, NCP4303B
Secondary Side
Synchronous Rectification
Driver for High Efficiency
SMPS Topologies
The NCP4303A/B is a full featured controller and driver tailored to
control synchronous rectification circuitry in switch mode power
supplies. Thanks to its versatility, it can be used in various topologies
such as flyback, forward and Half Bridge Resonant LLC.
The combination of externally adjustable minimum on and off times
helps to fight the ringing induced by the PCB layout and other
parasitic elements. Therefore, a reliable and noise less operation of the
SR system is insured.
The extremely low turn off delay time, high sink current capability
of the driver and automatic package parasitic inductance
compensation system allow to maximize synchronous rectification
MOSFET conduction time that enables further increase of SMPS
efficiency.
Finally, a wide operating V
CC
range combined with two versions of
driver voltage clamp eases implementation of the SR system in 24 V
output applications.
Features
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MARKING
DIAGRAM
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
4303x
ALYW
G
G
DFN8
CASE 488AF
1
4303x
NCP
4303x
ALYWG
G
•
Self-Contained Control of Synchronous Rectifier in CCM, DCM, and
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
QR Flyback Applications
Precise True Secondary Zero Current Detection with Adjustable
Threshold
Automatic Parasitic Inductance Compensation Input
Typically 40 ns Turn off Delay from Current Sense Input to Driver
Zero Current Detection Pin Capability up to 200 V
Optional Ultrafast Trigger Interface for Further Improved
Performance in Applications that Work in Deep CCM
Disable Input to Enter Standby or Low Consumption Mode
Adjustable Minimum On Time Independent of V
CC
Level
Adjustable Minimum Off Time Independent of V
CC
Level
5 A/2.5 A Peak Current Sink/Source Drive Capability
Operating Voltage Range up to 30 V
Gate Drive Clamp of Either 12 V (NCP4303A) or 6 V (NCP4303B)
Low Startup and Standby Current Consumption
Maximum Frequency of Operation up to 500 kHz
SOIC−8 Package
These are Pb-Free Devices
= Specific Device Code
x = A or B
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PINOUT INFORMATION
V
CC
Min_Toff
Min_Ton
Trig/Disable
1
2
3
4
8
7
6
5
DRV
GND
COMP
CS
(NOTE: For DFN the exposed pad must be either
unconnected or preferably connected to ground.
The GND pin must be always connected to ground.)
ORDERING INFORMATION
Device
NCP4303ADR2G
NCP4303BDR2G
NCP4303AMNTWG
Package
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
DFN8
(Pb−Free)
DFN8
(Pb−Free)
Shipping
†
2500 /
Tape & Reel
2500 /
Tape & Reel
4000 /
Tape & Reel
4000 /
Tape & Reel
Typical Applications
Notebook Adapters
High Power Density AC/DC Power Supplies
Gaming Consoles
All SMPS with High Efficiency Requirements
NCP4303BMNTWG
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2015
1
April, 2015 − Rev. 5
Publication Order Number:
NCP4303/D
NCP4303A, NCP4303B
Figure 1. Typical Application Example – LLC Converter
Figure 2. Typical Application Example − DCM, QR or CCM Flyback Converter
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2
NCP4303A, NCP4303B
PIN FUNCTION DESCRIPTION
Pin No.
1
2
3
4
Pin Name
VCC
Min_toff
Min_ton
TRIG/Disable
Function
Supplies the driver
Minimum off time adjust
Minimum on time adjust
Forced reset input
Pin Description
V
CC
supply terminal of the controller. Accepts up to 30 V continuously.
Adjust the minimum off time period by connecting resistor to ground.
Adjust the minimum on time period by connecting resistor to ground.
This ultrafast turn-off input offers the possibility to further improve efficiency
and performance in applications that work in deep Continuous Conduction
Mode (CCM). Activates sleep mode if pulled up for more than 100
ms.
Connect this pin to GND when not used.
This pin detects if the current flows through the SR MOSFET and/or its body
diode. Basic turn off detection threshold is 0 mV. A resistor in series with this
pin can modify the turn off threshold if needed.
Use as a Kelvin connection to auxiliary compensation inductance. If SR
MOSFET package parasitic inductance compensation is not used (like for
SMT MOSFETs), connect this pin directly to GND pin.
Ground connection for the SR MOSFET driver and V
CC
decoupling capacitor.
Ground connection for minimum ton, toff adjust resistors and trigger input.
GND pin should be wired directly to the SR MOSFET source
terminal/soldering point using Kelvin connection.
Driver output for the SR MOSFET.
5
CS
Current sense of the SR
MOSFET
Compensation inductance
connection
IC ground
6
COMP
7
GND
8
DRV
Gate driver output
Figure 3. Internal Circuit Architecture
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3
NCP4303A, NCP4303B
MAXIMUM RATINGS
Symbol
V
CC
V
DRV
V
CS
V
Csdyn
V
TRIG
V
Min_ton
, V
Min_toff
I
_Min_Toff
, I
_Min_Toff
VGND−COMP
VGND−COMP_dyn
ICOMP
R
qJA
R
qJA
R
qJA
T
Jmax
T
Smax
T
Lmax
IC supply voltage
Driver output voltage
Current sense input dc voltage
Current sense input dynamic voltage (t
pw
= 200 ns)
Trigger input voltage
Min_Ton and Min_Toff input voltage
Min_Ton and Min_Toff current
Static voltage difference between GND and COMP pins (internally clamped)
Dynamic voltage difference between GND and COMP pins (t
pw
= 200 ns)
Current into COMP pin
Thermal Resistance Junction−to−Air, SOIC version, A/B version
Thermal Resistance Junction−to−Air, DFN − A/B versions, 50 mm
2
− 1.0 oz.
Copper spreader
Thermal Resistance Junction−to−Air, DFN − A/B versions, 600 mm
2
− 1.0 oz.
Copper spreader
Maximum junction temperature
Storage Temperature Range
Lead temperature (Soldering, 10 s)
ESD Capability, Human Body Model except pin V
CS
– pin 5, HBM ESD
Capability on pin 5 is 650 V
ESD Capability, Machine Model
ESD Capability, Charged Device Model
Rating
Value
−0.3 to 30
−0.3 to 17
−4 to 200
−10 to 200
−0.3 to 10
−0.3 to 10
−10 to +10
−3 to 10
−10 to 10
−5 to 5
180
180
80
150
−60 to +150
300
2
200
250
Unit
V
V
V
V
V
V
mA
V
V
mA
°C/W
°C/W
°C/W
°C
°C
°C
kV
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Pin 1*8: Human Body Model 2000 V per JEDEC Standard JESD22−A114E
Machine Model Method 200 V per JEDEC Standard JESD22−A115−A
Charged Device Model 250 V per JEDEC Standard JESD22−C101E.
2. This device meets latchup tests defined by JEDEC Standard JESD78.
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4
NCP4303A, NCP4303B
ELECTRICAL CHARACTERISTICS
(For typical values T
J
= 25°C, for min/max values T
J
= −40°C to +125°C, Max T
J
= 150°C, V
CC
= 12 V, C
load
= 0 nF,
R
_min_ton
= R
_min_toff
= 10 kW, V
trig
= 0 V, f_CS = 100 kHz, DC_CS = 50%, V
CS_high
= 4 V, V
CS_low
= −1 V unless otherwise noted)
Symbol
SUPPLY SECTION
V
CC_on
V
CC_off
V
CC_hyste
I
CC1_A
I
CC1_B
I
CC2_A
I
CC2_B
I
CC3_A
I
CC3_B
I
CC_SDM
I
CC_SDM NS
DRIVE OUTPUT
t
r_A
t
r_B
t
f_A
t
f_B
R
oh
R
ol
I
DRV_pk(source)
I
DRV_pk(sink)
V
DRV(H)_A
V
DRV(H)_A
V
DRV(H)_B
V
DRV(H)_B
V
DRV(min_A)
V
DRV(min_B)
V
DRV(CLMP_A)
V
DRV(CLMP_B)
CS INPUT
T
pd_on
T
pd_off
I
shift_CS
V
th_cs_on
V
th_cs_off
The total propagation delay from CS input to DRV output turn on (V
CS
goes
down from 4 V to −1 V, t
f_CS
= 5 ns, COMP pin connected to GND)
The total propagation delay from CS input to DRV output turn off (V
CS
goes
up from −1 V to 4 V, t
r_CS
= 5 ns, COMP pin connected to GND), (Note 3)
Current sense input current source (V
CS
= 0 V)
Turn on current sense input threshold voltage
Current sense pin turn off threshold voltage, COMP pin connected to GND
(Note 3)
5, 8
5, 8
5
5, 8
5, 8
−
−
95
−120
−1
60
40
100
−85
−
90
55
105
−50
0
ns
ns
mA
mV
mV
Output voltage rise−time for A version (C
load
= 10 nF), (Note 3)
Output voltage rise−time for B version (C
load
= 10 nF), (Note 3)
Output voltage fall−time for A version (C
load
= 10 nF), (Note 3)
Output voltage fall−time for B version (C
load
= 10 nF), (Note 3)
Driver source resistance (Note 3)
Driver sink resistance
Output source peak current (Note 3)
Output sink peak current (Note 3)
Driver high level output voltage on A version (C
load
= 1 nF)
Driver high level output voltage on A version (C
load
= 10 nF)
Driver high level output voltage on B version (C
load
= 1 nF)
Driver high level output voltage on B version (C
load
= 10 nF)
Minimum drive output voltage for A version (V
CC
= V
CC_off
+ 200 mV)
Minimum drive output voltage for B version (V
CC
= V
CC_off
+ 200 mV)
Driver clamp voltage for A version,
(12 V < V
CC
< 28 V, minimum C
load
= 1 nF)
Driver clamp voltage for B version,
(12 V < V
CC
< 28 V, minimum C
load
= 1 nF)
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
−
−
−
−
−
−
−
−
10
11.8
5
6
8.3
4.5
−
−
120
80
50
35
1.8
1
2.5
5
−
−
−
−
−
−
12
7
−
−
−
−
7
2
−
−
−
−
−
−
−
−
16
8.3
ns
ns
ns
ns
W
W
A
A
V
V
V
V
V
V
V
V
Turn−on threshold level (V
CC
going up)
Minimum operating voltage after turn−on (V
CC
going down)
V
CC
hysteresis
Internal IC consumption (no output load on pin 8, F
sw
= 500 kHz,
R
Ton_min
= R
Toff_min
= 5 kW)
Internal IC consumption (C
load
= 1 nF on pin 8, F
sw
= 400 kHz,
R
Ton_min
= R
Toff_min
= 5 kW)
Internal IC consumption (C
load
= 10 nF on pin 8, F
sw
= 400 kHz,
R
Ton_min
= R
Toff_min
= 5 kW)
Startup current consumption (V
CC
= V
CC
_on − 0.1 V) and consumption
during light load (disable) mode, (F
sw
= 500 kHz, V
trig
= 5 V)
Startup current consumption (V
CC
= V
CC
_on − 0.1 V) and consumption
during light load (disable) mode, (V
cs
= 0 V, V
trig
= 5 V)
1
1
1
1
1
1
1
1
9.3
8.3
0.8
−
−
−
−
−
−
−
−
9.9
8.9
1.0
4.7
4
9.3
6.4
54
34
390
280
10.5
9.5
1.3
−
−
−
−
−
−
550
450
V
V
V
mA
mA
mA
mA
mA
Rating
Pin
Min
Typ
Max
Unit
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Guaranteed by design.
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