74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Rev. 01 — 29 May 2007
Product data sheet
1. General description
The 74LVC595A is an 8-bit serial-in/serial or parallel-out shift register with a storage
register and 3-state outputs. Both the shift and storage register have separate clocks.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial Power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
Data is shifted on the positive-going transitions of the SHCP input. The data in the shift
register is transferred to the storage register on a positive-going transition of the STCP
input. If both clocks are connected together, the shift register will always be one clock
pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial output (Q7S) for cascading
purposes. It is also provided with asynchronous reset input MR (active LOW) for all 8 shift
register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the
storage register appears at the output whenever the output enable input (OE) is LOW.
2. Features
s
s
s
s
s
s
s
s
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Balanced propagation delays
All inputs have Schmitt-trigger action
Complies with JEDEC standard JESD8-B/JESD36
ESD protection:
x
HBM JESD22-A114-D exceeds 2000 V
x
CDM JESD22-C101-C exceeds 1000 V
s
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C.
3. Applications
s
Serial-to-parallel data conversion
s
Remote control holding register
NXP Semiconductors
74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC595AD
74LVC595APW
74LVC595ABQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
SO16
TSSOP16
DHVQFN16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
Version
SOT109-1
Type number
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16
terminals; body 2.5
×
3.5
×
0.85 mm
SOT763-1
5. Functional diagram
11
12
9
15
1
2
3
4
5
6
7
13 OE
3-STATE OUTPUTS
Q
0
Q
1
Q
2
Q3 Q4 Q5 Q6 Q
7
mna552
SHCP STCP
Q7S
Q0
Q1
Q2
14
DS
Q3
Q4
Q5
Q6
Q7
MR
10
OE
13
14 DS
11 SHCP
10 MR
8-STAGE SHIFT REGISTER
Q7S
12 STCP
9
8-BIT STORAGE REGISTER
15 1
2
3
4
5
6
7
mna554
Fig 1. Logic symbol
Fig 2. Functional diagram
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
2 of 19
NXP Semiconductors
74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
STAGE 0
DS
D
FF0
CP
SHCP
R
Q
D
STAGES 1 TO 6
Q
STAGE 7
D
FF7
CP
R
Q
Q
7S
MR
D
Q
D
Q
LATCH
CP
STCP
OE
LATCH
CP
mna555
Q0
Q
1
Q2 Q3 Q4 Q5 Q6
Q7
Fig 3. Logic diagram
SHCP
DS
STCP
MR
OE
Q0
Q1
Z-state
Z-state
Q6
Q7
Q7 S
Z-state
Z-state
mna556
Fig 4. Timing diagram
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
3 of 19
NXP Semiconductors
74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
6. Pinning information
6.1 Pinning
74LVC595A
terminal 1
index area
16 V
CC
15 Q0
14 DS
13 OE
12 STCP
11 SHCP
10 MR
8
GND
Q7S
9
Q1
2
3
4
5
6
7
1
Q2
16 V
CC
15 Q0
14 DS
13 OE
12 STCP
11 SHCP
10 MR
9
001aaf569
74LVC595A
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
1
2
3
4
5
6
7
8
Q3
Q4
Q5
Q6
Q7
Q7S
001aaf570
Transparent top view
Fig 5. Pin configuration SO16 and TSSOP16
Fig 6. Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Symbol
Q[0:7]
GND
Q7S
MR
SHCP
STCP
OE
DS
V
CC
Pin description
Pin
15, 1, 2, 3, 4, 5, 6, 7
8
9
10
11
12
13
14
16
Description
parallel data output
ground (0 V)
serial data output
master reset (active LOW)
shift register clock input
storage register clock input
output enable input (active LOW)
serial data input
supply voltage
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
4 of 19
NXP Semiconductors
74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
7. Functional description
Table 3.
Input
SHCP STCP OE
X
X
X
↑
X
↑
X
X
L
L
H
L
MR
L
L
L
H
DS
X
X
X
H
Function table
[1]
Output
Q7S
L
L
L
Q6S
Qn
NC
L
Z
NC
a LOW-state on MR only affects the shift register
empty shift register loaded into storage register
shift register clear; parallel outputs in high impedance OFF-state
logic HIGH-state shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
Function
X
↑
↑
↑
L
L
H
H
X
X
NC
Q6S
QnS
QnS
[1]
H = HIGH voltage state;
L = LOW voltage state;
↑
= LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
−0.5
−50
−0.5
-
[1]
[1]
Max
+6.5
-
+6.5
±50
6.5
V
CC
+ 0.5
±50
100
-
+150
500
Unit
V
mA
V
mA
V
V
mA
mA
mA
°C
mW
V
O
> V
CC
or V
O
< 0 V
3-state
output HIGH or LOW state
V
O
= 0 V to V
CC
−0.5
−0.5
-
-
−100
−65
T
amb
=
−40 °C
to +125
°C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO16 packages: above 70
°C
the value of P
tot
derates linearly with 8 mW/K.
For TSSOP16 packages: above 60
°C
the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60
°C
the value of P
tot
derates linearly with 4.5 mW/K.
74LVC595A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 29 May 2007
5 of 19
stm32/stm8
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