74LVC3GU04
Triple inverter
Rev. 07 — 11 November 2009
Product data sheet
1. General description
The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered
output.
Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of
these devices in a mixed 3.3 V and 5 V environment.
2. Features
I
I
I
I
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
N
JESD8-7 (1.65 V to 1.95 V)
N
JESD8-5 (2.3 V to 2.7 V)
N
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
N
HBM JESD22-A114F exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
±24
mA output drive at V
CC
= 3.0 V
CMOS low power consumption
Latch-up performance exceeds 250 mA
Multiple package options
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C.
I
I
I
I
I
I
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC3GU04DP
74LVC3GU04DC
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
TSSOP8
VSSOP8
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
Version
SOT505-2
SOT765-1
Type number
NXP Semiconductors
74LVC3GU04
Triple inverter
Table 1.
Ordering information
…continued
Package
Temperature range
Name
XSON8
Description
plastic extremely thin small outline package; no leads;
8 terminals; body 1
×
1.95
×
0.5 mm
Version
SOT833-1
SOT996-2
SOT902-1
−40 °C
to +125
°C
−40 °C
to +125
°C
Type number
74LVC3GU04GT
74LVC3GU04GD
XSON8U plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3
×
2
×
0.5 mm
XQFN8U
plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6
×
1.6
×
0.5 mm
74LVC3GU04GM
−40 °C
to +125
°C
4. Marking
Table 2.
Marking codes
Marking code
[1]
VU04
VU4
VU4
VU4
VU4
Type number
74LVC3GU04DP
74LVC3GU04DC
74LVC3GU04GT
74LVC3GU04GD
74LVC3GU04GM
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1
1A
1Y
1
2A
2Y
1
3A
3Y
001aah793
001aah794
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
V
CC
V
CC
100
Ω
A
Y
mna636
Fig 3.
74LVC3GU04_7
Logic diagram (one gate)
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 11 November 2009
2 of 17
NXP Semiconductors
74LVC3GU04
Triple inverter
6. Pinning information
6.1 Pinning
74LVC3GU04
1A
1
8
V
CC
3Y
2
7
1Y
74LVC3GU04
2A
1A
3Y
2A
GND
1
2
3
4
mnb120
3
6
3A
8
7
6
5
V
CC
1Y
3A
2Y
GND
4
5
2Y
001aac021
Transparent top view
Fig 4.
Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Fig 5.
Pin configuration SOT833-1 (XSON8)
74LVC3GU04
terminal 1
index area
1Y
1
V
CC
8
74LVC3GU04
1A
3Y
2A
GND
1
2
3
4
8
7
6
5
V
CC
7
1A
3A
1Y
3A
2Y
2Y
2
6
3Y
3
4
5
2A
GND
001aag056
001aal098
Transparent top view
Transparent top view
Fig 6.
Pin configuration SOT996-2 (XSON8U)
Fig 7.
Pin configuration SOT902-1 (XQFN8U)
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
SOT505-2, SOT765-1,
SOT833-1 and SOT996-2
1A, 2A, 3A
GND
1Y, 2Y, 3Y
V
CC
1, 3, 6
4
7, 5, 2
8
SOT902-1
7, 5, 2
4
1, 3, 6
8
data input
ground (0 V)
data output
supply voltage
Description
74LVC3GU04_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 11 November 2009
3 of 17
NXP Semiconductors
74LVC3GU04
Triple inverter
7. Functional description
Table 4.
Input nA
L
H
[1]
H = HIGH voltage level; L = LOW voltage level.
Function table
[1]
Output nY
H
L
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
P
tot
T
stg
[1]
[2]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
supply current
ground current
total power dissipation
storage temperature
Conditions
[1]
Min
−0.5
−0.5
−0.5
−50
-
-
-
−100
Max
+6.5
+6.5
V
CC
+ 0.5
-
±50
±50
100
-
250
+150
Unit
V
V
V
mA
mA
mA
mA
mA
mW
°C
Active mode
V
I
< 0 V
V
O
> V
CC
or V
O
< 0 V
V
O
= 0 V to V
CC
[1]
T
amb
=
−40 °C
to +125
°C
[2]
-
−65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For TSSOP8 packages: above 55
°C
the value of P
tot
derates linearly with 2.5 mW/K.
For VSSOP8 packages: above 110
°C
the value of P
tot
derates linearly with 8.0 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 45
°C
the value of P
tot
derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
1.65
0
0
0
−40
-
-
Max
5.5
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
°C
ns/V
ns/V
74LVC3GU04_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 11 November 2009
4 of 17
NXP Semiconductors
74LVC3GU04
Triple inverter
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
Conditions
V
CC
= 1.65 V to 5.5 V
V
CC
= 1.65 V to 5.5 V
V
I
= V
IH
or V
IL
I
O
=
−100 µA;
V
CC
= 1.65 V to 5.5 V
I
O
=
−4
mA; V
CC
= 1.65 V
I
O
=
−8
mA; V
CC
= 2.3 V
I
O
=
−12
mA; V
CC
= 2.7 V
I
O
=
−24
mA; V
CC
= 3.0 V
I
O
=
−32
mA; V
CC
= 4.5 V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 100
µA;
V
CC
= 1.65 V to 5.5 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
O
= 32 mA; V
CC
= 4.5 V
I
I
I
CC
C
I
V
IH
V
IL
V
OH
input leakage current
supply current
input capacitance
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
V
CC
= 1.65 V to 5.5 V
V
CC
= 1.65 V to 5.5 V
V
I
= V
IH
or V
IL
I
O
=
−100 µA;
V
CC
= 1.65 V to 5.5 V
I
O
=
−4
mA; V
CC
= 1.65 V
I
O
=
−8
mA; V
CC
= 2.3 V
I
O
=
−12
mA; V
CC
= 2.7 V
I
O
=
−24
mA; V
CC
= 3.0 V
I
O
=
−32
mA; V
CC
= 4.5 V
V
CC
−
0.1
0.95
1.7
1.9
2.0
3.4
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
V
I
= 5.5 V or GND;
V
CC
= 1.65 V to 5.5 V; I
O
= 0 A
-
-
-
-
-
-
-
-
-
0.8
×
V
CC
-
-
-
-
-
-
-
±0.1
0.1
5
-
-
0.1
0.45
0.3
0.4
0.55
0.55
±5
10
-
-
0.2
×
V
CC
V
V
V
V
V
V
µA
µA
pF
V
V
V
CC
−
0.1
1.2
1.9
2.2
2.3
3.8
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
Min
Typ
[1]
Max
-
Unit
V
T
amb
=
−40 °C
to +85
°C
0.75
×
V
CC
-
-
-
0.25
×
V
CC
V
T
amb
=
−40 °C
to +125
°C
74LVC3GU04_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 11 November 2009
5 of 17
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
