74LVC3G06
Triple inverter with open-drain output
Rev. 07 — 12 March 2009
Product data sheet
1. General description
The 74LVC3G06 provides three inverting buffers.
The output of this device is an open drain and can be connected to other open-drain
outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall
time.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features
I
I
I
I
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
N
JESD8-7 (1.65 V to 1.95 V)
N
JESD8-5 (2.3 V to 2.7 V)
N
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
−24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
I
I
I
I
I
I
I
I
NXP Semiconductors
74LVC3G06
Triple inverter with open-drain output
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVC3G06DP
74LVC3G06DC
74LVC3G06GT
74LVC3G06GD
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
TSSOP8
VSSOP8
XSON8
XSON8U
Description
plastic thin shrink small outline package;
8 leads; body width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
plastic extremely thin small outline package;
no leads; 8 terminals; body 1
×
1.95
×
0.5 mm
plastic extremely thin small outline package; no
leads; 8 terminals; UTLP based; body 3
×
2
×
0.5
mm
plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6
×
1.6
×
0.5 mm
Version
SOT505-2
SOT765-1
SOT833-1
SOT996-2
Type number
74LVC3G06GM
−40 °C
to +125
°C
XQFN8U
SOT902-1
4. Marking
Table 2.
Marking codes
Marking code
V06
V06
V06
V06
V06
Type number
74LVC3G06DP
74LVC3G06DC
74LVC3G06GT
74LVC3G06GD
74LVC3G06GM
5. Functional diagram
1
1A
1Y
1
2A
2Y
Y
3A
3Y
1
A
001aah899
001aah900
GND
mna586
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one driver)
74LVC3G06_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 12 March 2009
2 of 16
NXP Semiconductors
74LVC3G06
Triple inverter with open-drain output
6. Pinning information
6.1 Pinning
74LVC3G06
1A
1
8
V
CC
3Y
2
7
1Y
74LVC3G06
1A
3Y
2A
GND
1
2
3
4
001aab841
8
7
6
5
V
CC
1Y
3A
2Y
2A
3
6
3A
GND
4
5
2Y
001aab842
Transparent top view
Fig 4. Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Fig 5. Pin configuration SOT833-1 (XSON8)
74LVC3G06
terminal 1
index area
1Y
1
V
CC
8
74LVC3G06
1A
3Y
2A
GND
1
2
3
4
8
7
6
5
V
CC
7
1A
3A
1Y
3A
2Y
2Y
2
6
3Y
3
4
5
2A
GND
001aag242
001aaj791
Transparent top view
Transparent top view
Fig 6.
Pin configuration SOT996-2 (XSON8U)
Fig 7.
Pin configuration SOT902-1 (XQFN8U)
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
SOT505-2, SOT765-1,
SOT833-1 and SOT996-2
1A, 2A, 3A
1Y, 2Y, 3Y
GND
V
CC
1, 3, 6
7, 5, 2
4
8
SOT902-1
7, 5, 2
1, 3, 6
4
8
data input
data output
ground (0 V)
supply voltage
Description
74LVC3G06_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 12 March 2009
3 of 16
NXP Semiconductors
74LVC3G06
Triple inverter with open-drain output
7. Functional description
Table 4.
Input nA
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
Function table
[1]
Output nY
Z
L
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
−0.5
−50
−0.5
−50
[1]
[1][2]
Max
+6.5
-
+6.5
-
+6.5
+6.5
50
100
-
+150
250
Unit
V
mA
V
mA
V
V
mA
mA
mA
°C
mW
V
O
< 0 V
Active mode
Power-down mode
V
O
= 0 V to 6.5 V
−0.5
−0.5
-
-
−100
−65
T
amb
=
−40 °C
to +125
°C
[3]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
For TSSOP8 and VSSOP8 packages: above 110
°C
the value of P
tot
derates linearly at 8.0 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 45
°C
the value of P
tot
derates linearly at 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
1.65
0
0
0
−40
-
-
Max
5.5
5.5
5.5
5.5
+125
20
10
Unit
V
V
V
V
°C
ns/V
ns/V
74LVC3G06_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 12 March 2009
4 of 16
NXP Semiconductors
74LVC3G06
Triple inverter with open-drain output
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
V
IH
Parameter
HIGH-level input
voltage
Conditions
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input
voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OL
LOW-level output
voltage
V
I
= V
IH
or V
IL
I
O
= 100
µA;
V
CC
= 1.65 V to 5.5 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
O
= 32 mA; V
CC
= 4.5 V
I
I
I
OZ
I
OFF
I
CC
∆I
CC
C
I
input leakage current V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
OFF-state output
current
power-off leakage
current
supply current
additional supply
current
input capacitance
V
I
= V
IH
or V
IL
; V
O
= V
CC
or GND;
V
CC
= 5.5 V
V
I
or V
O
= 5.5 V; V
CC
= 0 V
V
I
= 5.5 V or GND; I
O
= 0 A;
V
CC
= 1.65 V to 5.5 V
per pin; V
I
= V
CC
−
0.6 V; I
O
= 0 A;
V
CC
= 2.3 V to 5.5 V
[2]
[2]
Min
Typ
Max
-
-
-
-
0.7
0.8
0.3
×
V
CC
0.10
0.45
0.30
0.40
0.55
0.55
±5
±10
±10
10
500
-
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
pF
T
amb
=
−40 °C
to +85
°C
[1]
0.65
×
V
CC
-
1.7
2.0
0.7
×
V
CC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±0.1
±0.1
±0.1
0.1
5
2.5
0.35
×
V
CC
V
74LVC3G06_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 12 March 2009
5 of 16
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