74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Rev. 03 — 21 May 2007
Product data sheet
1. General description
The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type
flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q
output.
The master reset (MR) is an asynchronous active LOW input and operates independently
of the clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time
prior to the LOW-to-HIGH clock transition for predictable operation.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
2. Features
s
s
s
s
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
x
JESD8-7 (1.65 V to 1.95 V)
x
JESD8-5 (2.3 V to 2.7 V)
x
JESD8B/JESD36 (2.7 V to 3.6 V).
±24
mA output drive (V
CC
= 3.0 V)
ESD protection:
x
HBM JESD22-A114E exceeds 2000 V
x
MM JESD22-A115-A exceeds 200 V.
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C.
s
s
s
s
s
s
s
s
NXP Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVC1G175GW
74LVC1G175GV
74LVC1G175GM
74LVC1G175GF
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
SC-88
SC-74
XSON6
XSON6
Description
plastic surface-mounted package; 6 leads
plastic surface-mounted package (TSOP6); 6 leads
plastic extremely thin small outline package;
no leads; 6 terminals; body 1
×
1.45
×
0.5 mm
plastic extremely thin small outline package;
no leads; 6 terminals; body 1
×
1
×
0.5 mm
Version
SOT363
SOT457
SOT886
SOT891
Type number
4. Marking
Table 2.
Marking
Marking code
YT
V75
YT
YT
Type number
74LVC1G175GW
74LVC1G175GV
74LVC1G175GM
74LVC1G175GF
5. Functional diagram
6
3
MR
D
FF
Q
4
CP
001aaa468
1
3
6
CP
D
MR
001aaa469
1
Q
4
Fig 1. Logic symbol.
Fig 2. IEC logic symbol.
CP
C
C
C
C
Q
C
D
C
MR
C
C
C
C
001aaa466
Fig 3. Logic diagram.
74LVC1G175_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 21 May 2007
2 of 17
NXP Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
6. Pinning information
6.1 Pinning
74LVC1G175
74LVC1G175
CP
GND
1
2
6
5
MR
GND
V
CC
D
D
3
001aag506
CP
1
6
MR
CP
GND
74LVC1G175
1
2
3
6
5
4
MR
V
CC
Q
2
5
V
CC
3
4
Q
D
4
Q
001aag507
001aag508
Transparent top view
Transparent top view
Fig 4. Pin configuration SOT363
and SOT457
Fig 5. Pin configuration SOT886
Fig 6. Pin configuration SOT891
6.2 Pin description
Table 3.
Symbol
CP
GND
D
Q
V
CC
MR
Pin description
Pin
1
2
3
4
5
6
Description
clock input (LOW-to-HIGH, edge-triggered)
ground (0 V)
data input
flip-flop output
supply voltage
master reset input (active LOW)
7. Functional description
Table 4.
Function table
[1]
Input
MR
Reset (clear)
Load ‘1’
Load ‘0’
[1]
Operating mode
Output
CP
X
↑
↑
D
X
h
l
Q
L
H
L
L
H
H
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
↑
= LOW-to-HIGH CP transition;
X = don’t care.
74LVC1G175_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 21 May 2007
3 of 17
NXP Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
P
tot
T
stg
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
total power dissipation
storage temperature
Conditions
V
I
< 0 V
[1]
Min
−0.5
−50
−0.5
-
[1][2]
[1][2]
Max
+6.5
-
+6.5
±50
V
CC
+ 0.5
+6.5
±50
100
-
250
+150
Unit
V
mA
V
mA
V
V
mA
mA
mA
mW
°C
V
O
> V
CC
or V
O
< 0 V
Active mode
Power-down mode
V
O
= 0 V to V
CC
−0.5
−0.5
-
-
−100
T
amb
=
−40 °C
to +125
°C
[3]
-
−65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
For SC-88 and SC-74A packages: above 87.5
°C
the value of P
tot
derates linearly with 4.0 mW/K.
For XSON6 packages: above 45
°C
the value of P
tot
derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
1.65
0
0
0
−40
-
-
Typ
-
-
-
-
-
-
-
Max
5.5
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
°C
ns/V
ns/V
74LVC1G175_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 21 May 2007
4 of 17
NXP Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
=
−40 °C
to +85
°C
[1]
V
IH
HIGH-level input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
−100 µA;
V
CC
= 1.65 V to 5.5 V
I
O
=
−4
mA; V
CC
= 1.65 V
I
O
=
−8
mA; V
CC
= 2.3 V
I
O
=
−12
mA; V
CC
= 2.7 V
I
O
=
−24
mA; V
CC
= 3.0 V
I
O
=
−32
mA; V
CC
= 4.5 V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 100
µA;
V
CC
= 1.65 V to 5.5 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
O
= 32 mA; V
CC
= 4.5 V
I
I
I
OFF
I
CC
∆I
CC
C
I
input leakage current
power-off leakage current
supply current
additional supply current
input capacitance
V
CC
= 0 V to 5.5 V; V
I
= 5.5 V or GND
V
CC
= 0 V; V
I
or V
O
= 5.5 V
V
CC
= 1.65 V to 5.5 V; I
O
= 0 A;
V
I
= 5.5 V or GND
V
CC
= 2.3 V to 5.5 V; V
I
= V
CC
−
0.6 V;
I
O
= 0 A
V
CC
= 3.3 V; V
I
= GND to V
CC
[2]
[2]
Conditions
Min
0.65
×
V
CC
1.7
2.0
0.7
×
V
CC
-
-
-
-
V
CC
−
0.1
1.2
1.9
2.2
2.3
3.8
-
-
-
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
1.54
2.15
2.50
2.62
4.11
-
0.07
0.12
0.17
0.33
0.39
±0.1
±0.1
0.1
5
2.5
Max
-
-
-
-
0.35
×
V
CC
0.7
0.8
0.3
×
V
CC
-
-
-
-
-
-
0.10
0.45
0.30
0.40
0.55
0.55
±5
±10
10
500
-
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
pF
74LVC1G175_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 21 May 2007
5 of 17
嵌入式系统
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