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74LVC16374A: 产品描述Quadruple 2-Line To 1-Line Data Selectors/Multiplexers With 3-State Outputs 16-SOIC -40 to 85; 文件大小143KB，共19页; 制造商NXP(恩智浦); 官网地址https://www.nxp.com

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74LVC16374A概述

Quadruple 2-Line To 1-Line Data Selectors/Multiplexers With 3-State Outputs 16-SOIC -40 to 85

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74LVC16374A; 74LVCH16374A

16-bit edge-triggered D-type flip-flop with 5 V tolerant

inputs/outputs; 3-state

Rev. 07 — 23 March 2010

Product data sheet

1. General description

The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring

separate D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state

outputs for bus oriented applications. It consists of two sections of eight positive

edge-triggered flip-flops. A clock input (nCP) and an output enable (nOE) are provided for

each octal.

The flip-flops will store the state of their individual D-inputs that meet the set-up and hold

time requirements on the LOW-to-HIGH clock (CP) transition.

When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin

nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE

does not affect the state of the flip-flops.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be

applied to the outputs. These features allow the use of these devices in mixed 3.3 V and

5 V applications.

Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused

inputs.

2. Features and benefits

5 V tolerant inputs/outputs for interfacing with 5 V logic

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low power consumption

Multibyte flow-through standard pin-out architecture

Low inductance multiple supply pins for minimum noise and ground bounce

Direct interface with TTL levels

All data inputs have bus hold (74LVCH16374A only)

High-impedance outputs when V

= 0 V

Complies with JEDEC standard JESD8-B/JESD36

ESD protection:

HBM JESD22-A114F exceeds 2000 V

CDM JESD22-C101D exceeds 1000 V

Specified from

−40 °C

to +85

°C

and

−40 °C

to +125

°C

74LVC16374A相似产品对比

	74LVC16374A	74LVC16374ABQ	74LVCH16374A	74LVCH16374ADGG	74LVCH16374ABQ
描述	Quadruple 2-Line To 1-Line Data Selectors/Multiplexers With 3-State Outputs 16-SOIC -40 to 85	Quadruple 2-Line To 1-Line Data Selectors/Multiplexers With 3-State Outputs 16-SOIC -40 to 85	14-Bit Asynchronous Binary Counters 16-SOIC -40 to 85	Quadruple 2-Line To 1-Line Data Selectors/Multiplexers With 3-State Outputs 16-SOIC -40 to 85	Quadruple 2-Line To 1-Line Data Selectors/Multiplexers With 3-State Outputs 16-SOIC -40 to 85
是否Rohs认证	-	符合	-	符合	符合
厂商名称	-	NXP(恩智浦)	-	NXP(恩智浦)	NXP(恩智浦)
零件包装代码	-	QFN	-	TSSOP	QFN
包装说明	-	4 X 6 MM, 0.55 MM PITCH, PLASTIC, SOT1025-1, HXQFN-60	-	TSSOP, TSSOP48,.3,20	4 X 6 MM, 0.55 MM PITCH, PLASTIC, SOT1025-1, HXQFN-60
针数	-	60	-	48	60
Reach Compliance Code	-	compli	-	compli	compli
系列	-	LVC/LCX/Z	-	LVC/LCX/Z	LVC/LCX/Z
JESD-30 代码	-	R-PBCC-B60	-	R-PDSO-G48	R-PBCC-B60
JESD-609代码	-	e4	-	e4	e4
长度	-	6 mm	-	12.5 mm	6 mm
负载电容（CL）	-	50 pF	-	50 pF	50 pF
逻辑集成电路类型	-	BUS DRIVER	-	BUS DRIVER	BUS DRIVER
最大频率@ Nom-Su	-	100000000 Hz	-	100000000 Hz	100000000 Hz
最大I（ol）	-	0.024 A	-	0.024 A	0.024 A
湿度敏感等级	-	2	-	1	2
位数	-	8	-	8	8
功能数量	-	2	-	2	2
端口数量	-	2	-	2	2
端子数量	-	60	-	48	60
最高工作温度	-	125 °C	-	125 °C	125 °C
最低工作温度	-	-40 °C	-	-40 °C	-40 °C
输出特性	-	3-STATE	-	3-STATE	3-STATE
输出极性	-	TRUE	-	TRUE	TRUE
封装主体材料	-	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	-	HVBCC	-	TSSOP	HVBCC
封装等效代码	-	LCC(UNSPEC)	-	TSSOP48,.3,20	LCC(UNSPEC)
封装形状	-	RECTANGULAR	-	RECTANGULAR	RECTANGULAR
封装形式	-	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	-	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
电源	-	3.3 V	-	3.3 V	3.3 V
Prop。Delay @ Nom-Su	-	7 ns	-	7 ns	7 ns
传播延迟（tpd）	-	7.5 ns	-	7.5 ns	7.5 ns
认证状态	-	Not Qualified	-	Not Qualified	Not Qualified
座面最大高度	-	0.6 mm	-	1.2 mm	0.6 mm
最大供电电压 (Vsup)	-	3.6 V	-	3.6 V	3.6 V
最小供电电压 (Vsup)	-	1.2 V	-	1.2 V	1.2 V
标称供电电压 (Vsup)	-	2.7 V	-	2.7 V	2.7 V
表面贴装	-	YES	-	YES	YES
技术	-	CMOS	-	CMOS	CMOS
温度等级	-	AUTOMOTIVE	-	AUTOMOTIVE	AUTOMOTIVE
端子面层	-	Nickel/Palladium/Gold (Ni/Pd/Au)	-	NICKEL PALLADIUM GOLD	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式	-	BUTT	-	GULL WING	BUTT
端子节距	-	0.5 mm	-	0.5 mm	0.5 mm
端子位置	-	BOTTOM	-	DUAL	BOTTOM
触发器类型	-	POSITIVE EDGE	-	POSITIVE EDGE	POSITIVE EDGE
宽度	-	4 mm	-	6.1 mm	4 mm

74LVC16374A

74LVC16374A概述

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