SN54HC191, SN74HC191
4 BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121D − DECEMBER 1982 − REVISED OCTOBER 2003
D
D
D
D
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Max I
CC
Typical t
pd
= 13 ns
±4-mA
Output Drive at 5 V
Low Input Current of 1
µA
Max
Single Down/Up Count-Control Line
Look-Ahead Circuitry Enhances Speed of
Cascaded Counters
Fully Synchronous in Count Modes
Asynchronously Presettable With Load
Control
SN54HC191 . . . J OR W PACKAGE
SN74HC191 . . . D, N, OR NS PACKAGE
(TOP VIEW)
B
Q
B
Q
A
CTEN
D/U
Q
C
Q
D
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
A
CLK
RCO
MAX/MIN
LOAD
C
D
SN54HC191 . . . FK PACKAGE
(TOP VIEW)
The outputs of the four flip-flops are triggered on
a low- to high-level transition of the clock (CLK)
input if the count-enable (CTEN) input is low. A
high at CTEN inhibits counting. The direction of
the count is determined by the level of the
down/up (D/U) input. When D/U is low, the counter
counts up, and when D/U is high, it counts down.
NC − No internal connection
ORDERING INFORMATION
TA
PDIP − N
PACKAGE†
Tube of 25
Tube of 40
−40 C 85°C
−40°C to 85 C
SOIC − D
SOP − NS
CDIP − J
−55°C to 125 C
−55 C 125°C
CFP − W
LCCC − FK
Reel of 2500
Reel of 250
Reel of 2000
Tube of 25
Tube of 150
Tube of 55
ORDERABLE
PART NUMBER
SN74HC191N
SN74HC191D
SN74HC191DR
SN74HC191DT
SN74HC191NSR
SNJ54HC191J
SNJ54HC191W
SNJ54HC191FK
HC191
SNJ54HC191J
SNJ54HC191W
SNJ54HC191FK
HC191
TOP-SIDE
MARKING
SN74HC191N
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
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•
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Q
D
GND
NC
D
C
The ’HC191 devices are 4-bit synchronous,
reversible,
up/down
binary
counters.
Synchronous counting operation is provided by
having all flip-flops clocked simultaneously so that
the outputs change coincident with each other
when instructed by the steering logic. This mode
of operation eliminates the output counting spikes
normally
associated
with
asynchronous
(ripple-clock) counters.
Q
B
B
NC
V
CC
A
Q
A
CTEN
NC
D/U
Q
C
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
description/ordering information
CLK
RCO
NC
MAX/MIN
LOAD
1
SN54HC191, SN74HC191
4 BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121D − DECEMBER 1982 − REVISED OCTOBER 2003
description/ordering information (continued)
These counters feature a fully independent clock circuit. Change at the control (CTEN and D/U) inputs that
modifies the operating mode have no effect on the contents of the counter until clocking occurs. The function
of the counter is dictated solely by the condition meeting the stable setup and hold times.
These counters are fully programmable; that is, each of the outputs can be preset to either level by placing a
low on the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with
the data inputs independently of the level of CLK. This feature allows the counters to be used as modulo-N
dividers simply by modifying the count length with the preset inputs.
Two outputs are available to perform the cascading function: ripple clock (RCO) and maximum/minimum
(MAX/MIN) count. MAX/MIN produces a high-level output pulse with a duration approximately equal to one
complete cycle of the clock while the count is zero (all outputs low) counting down, or maximum (9 or 15)
counting up. RCO produces a low-level output pulse under those same conditions, but only while CLK is low.
The counters can be cascaded easily by feeding RCO to CTEN of the succeeding counter if parallel clocking
is used, or to CLK if parallel enabling is used. MAX/MIN can be used to accomplish look ahead for high-speed
operation.
2
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SN54HC191, SN74HC191
4 BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121D − DECEMBER 1982 − REVISED OCTOBER 2003
logic diagram (positive logic)
12
4
13
D/U
CLK
LOAD
A
5
14
11
15
S
C1
1D
R
1
2
3
RCO
MAX/MIN
CTEN
QA
B
S
C1
1D
R
QB
C
10
6
S
C1
1D
R
QC
D
9
7
S
C1
1D
R
QD
Pin numbers shown are for the D, J, N, NS, and W packages.
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3
SN54HC191, SN74HC191
4 BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121D − DECEMBER 1982 − REVISED OCTOBER 2003
typical load, count, and inhibit sequence
The following sequence is illustrated below:
1. Load (preset) to binary 13
2. Count up to 14, 15 (maximum), 0, 1, and 2
3. Inhibit
4. Count down to 1, 0 (minimum), 15, 14, and 13
LOAD
A
B
C
D
Data
Inputs
CLK
D/U
CTEN
QA
QB
QC
QD
MAX/MIN
RCO
13
14
15
0
1
2
2
2
1
0
15
14
13
Data
Outputs
Count Up
Inhibit
Load
Count Down
4
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SN54HC191, SN74HC191
4 BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121D − DECEMBER 1982 − REVISED OCTOBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC191
MIN
VCC
VIH
Supply voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VO
∆t/∆v
‡
Low-level input voltage
Input voltage
Output voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 4.5 V
VCC = 6 V
0
0
2
1.5
3.15
4.2
0.5
1.35
1.8
VCC
VCC
1000
500
400
0
0
NOM
5
MAX
6
SN74HC191
MIN
2
1.5
3.15
4.2
0.5
1.35
1.8
VCC
VCC
1000
500
400
ns
V
V
V
V
NOM
5
MAX
6
UNIT
V
High-level input voltage
Input transition rise/fall time
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
‡ If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
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•
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5
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