74AUP1T1326
Low-power dual supply buffer/line driver; 3-state
Rev. 01 — 20 January 2009
Product data sheet
1. General description
The 74AUP1T1326 is a high-performance, low-power, low-voltage, single-bit, dual supply
buffer/line driver with output enable circuitry.
The 74AUP1T1326 is designed for logic-level translation applications and combines the
functions of the 74AUP1G32 and 74AUP1G126. The buffer/line driver is controlled by two
output enable Schmitt trigger inputs (1OE and 2OE) through an OR-gate. The output
enable inputs accept standard input signals and are capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals. The output of the
OR-gate is also available at output 1Y.
The output enable inputs (1OE and 2OE) switch at different points for positive and
negative-going signals. The difference between the positive voltage V
T+
and the negative
voltage V
T−
is defined as the input hysteresis voltage V
H
.
Both V
CC(A)
and V
CC(B)
can be supplied at any voltage between 1.1 V and 3.6 V making
the device suitable for interfacing between any of the low voltage nodes (1.2 V, 1.5 V,
1.8 V, 2.5 V and 3.3 V) with compatible input levels. Pins 1OE, 2OE and 1Y are referenced
to V
CC(A)
and pins A and 2Y are referenced to V
CC(B)
. A logic LOW on both output enable
pins causes the output 2Y to assume a high-impedance OFF-state.
The device ensures low static and dynamic power consumption and is fully specified for
partial power down applications using I
OFF
. The I
OFF
circuitry disables the outputs,
preventing any damaging backflow current through the device when it is powered down.
2. Features
I
Wide supply voltage range:
N
V
CC(A)
: 1.1 V to 3.6 V; V
CC(B)
: 1.1 V to 3.6 V.
I
High noise immunity
I
Complies with JEDEC standards:
N
JESD8-7 (1.2 V to 1.95 V)
N
JESD8-5 (1.8 V to 2.7 V)
N
JESD8-B (2.7 V to 3.6 V)
I
ESD protection:
N
HBM JESD22-A114E Class 2A exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Low static power consumption; I
CC
= 0.9
µA
(maximum)
I
Latch-up performance exceeds 100 mA per JESD 78 Class II
I
Inputs accept voltages up to 3.6 V
NXP Semiconductors
74AUP1T1326
Low-power dual supply buffer/line driver; 3-state
I
I
I
I
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
−40 °C
to +85
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AUP1T1326GT
−40 °C
to +85
°C
XSON8
Description
Version
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 x 1.95 x 0.5 mm
Type number
4. Marking
Table 2.
Marking
Marking code
p31
Type number
74AUP1T1326GT
5. Functional diagram
1OE
5
Rpd
7
1Y
2OE
6
Rpd
V
CC(A)
A
2
V
CC(B)
8
2Y
001aaj293
R
pd
= Internal pull-down resistor.
Fig 1.
Logic symbol
74AUP1T1326_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 20 January 2009
2 of 24
NXP Semiconductors
74AUP1T1326
Low-power dual supply buffer/line driver; 3-state
6. Pinning information
6.1 Pinning
74AUP1T1326
V
CC(B)
1
8
2Y
A
2
7
1Y
V
CC(A)
3
6
2OE
GND
4
5
1OE
001aaj294
Transparent top view
Fig 2.
Pin configuration SOT833-1 (XSON8)
6.2 Pin description
Table 3.
Symbol
V
CC(B)
A
V
CC(A)
GND
1OE
2OE
1Y
2Y
Pin description
Pin
1
2
3
4
5
6
7
8
Description
supply voltage B
data input
supply voltage A
ground (0 V)
output enable input (Schmitt trigger input)
output enable input (Schmitt trigger input)
data output
data output
7. Functional description
Table 4.
Input
1OE
L
X
X
H
H
[1]
Function table
[1]
Output
2OE
L
H
H
X
X
A
X
L
H
L
H
1Y
L
H
H
H
H
2Y
Z
L
H
L
H
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
74AUP1T1326_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 20 January 2009
3 of 24
NXP Semiconductors
74AUP1T1326
Low-power dual supply buffer/line driver; 3-state
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC(A)
V
CC(B)
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage A
supply voltage B
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
−0.5
−0.5
Max
+4.6
+4.6
-
+4.6
−50
+4.6
±20
50
-
+150
250
Unit
V
V
mA
V
mA
V
mA
mA
mA
°C
mW
V
I
< 0 V
[1]
-50
−0.5
-
−0.5
-
-
-50
−65
[2]
[1]
[2]
V
O
> V
CCO
or V
O
< 0 V
Active mode and Power-down mode
V
O
= 0 V to V
CCO
T
amb
=
−40 °C
to +85
°C
[3]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
V
CCO
is the supply voltage associated with an output pin.
For XSON8 package: above 45
°C
the value of P
tot
derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC(A)
V
CC(B)
V
I
V
O
T
amb
∆t/∆V
Recommended operating conditions
Parameter
supply voltage A
supply voltage B
input voltage
output voltage
ambient temperature
input transition rise and fall rate
input A; V
CCI
= 1.1 V to 3.6 V
input nOE;
V
CCI
= 1.1 V to 3.6 V
[1]
[2]
V
CCO
is the supply voltage associated with an output pin.
V
CCI
is the supply voltage associated with an input pin.
[2]
[2]
[1]
Conditions
Min
1.1
1.1
0
0
−40
-
-
Max
3.6
3.6
3.6
V
CCO
+85
200
30
Unit
V
V
V
V
°C
ns/V
ms/V
74AUP1T1326_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 20 January 2009
4 of 24
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