SM8223A
NIPPON PRECISION CIRCUITS INC.
FSK Decoder and DTMF Receiver IC
OVERVIEW
The SM8223A is a FSK (Frequency shift keying) decoder and DTMF (Dual tone multi-frequency) receiver IC.
It is fabricated using a CMOS process and features a power-down function for low power dissipation opera-
tion. The FSK decoder and DTMF receiver have the same performance characteristics as dedicated ICs that
perform the same functions, with the added benefit of an FSK decoder/DTMF receiver auto-select function
1
using the telephone tip/ring input signal. It also features a ring (call signal) signal detection circuit, making for
easy construction of low power dissipation, high-performance analog telephone-related applications.
FEATURES
s
PINOUT
(Top view)
s
s
s
s
s
s
s
s
Both FSK signal caller-ID information services
and DTMF signal caller-ID information services
supported
FSK decoder/DTMF receiver auto-select function
Ring (call signal) signal detection circuit built-in
Serial I/O
Input gain adjustment circuit built-in
Power-down mode
Single supply operation: 3.0V ± 10%
3.579545MHz external crystal oscillator fre-
quency
Molybdenum-gate CMOS process
TIP
RING
GS
AGND
RDIN
RDRC
RDET
PDWN
1
16
VDD
DV
DOUT
FSK/DTMF
IC
OSCIN
OSCOUT
SM8223AP
8
9
GND
APPLICATIONS
s
s
s
Telephones, fax machines and modems that sup-
port caller-ID information services
Adapters for caller-ID information service func-
tions
Telephones, fax machines and modems that sup-
port remote operation functions
PINOUT
(Unit:
µm)
RING
TIP
VDD
DV
(2810, 3160)
ORDERING INFORMATION
D e vice
SM8223A
CF8223A
P ackag e
16-pin DIP
Chip
GS
DOUT
AGND
FSK/DTMF
RDIN
IC
RDRC
OSCIN
(0, 0)
RDET
PDWN
GND OSCOUT
P ad size : 90µm
×
90µm
1. Auto-select function operates if the FSK signal conforms to the Bellcore GR-30-CORE standard.
NIPPON PRECISION CIRCUITS—1
SM8223A
PACKAGE DIMENSIONS
(Unit: mm)
7.49 to 8.13
3.18
3.30
2.54
0.46
1.52
BLOCK DIAGRAM
FSK/DTMF
Differential
Amplifier
TIP
RING
GS
FSK Decoder
DV
Band Pass
Filter
FSK
Decoder
Logic
DOUT
FSK/DTMF
Discriminator
Logic
High Group
Filter
Dial Tone
Filter
Low Group
Filter
DTMF
Decoder
Logic
DTMF Receiver
AGND
Bias
Circuit
OSC
0.38 to 1.02
3.68 to 4.32
Ring Detect
VDD GND PDWN
OSCIN
OSCOUT
RDIN
RDRC
NIPPON PRECISION CIRCUITS—2
0.25
19.05
RDET
8.13 to 9.40
6.35
SM8223A
PIN DESCRIPTION
P ad dimensions (µm )
Number
1
2
3
4
5
6
7
Name
TIP
RING
GS
AG N D
RDIN
RDRC
RDET
I/O
I
I
O
O
I
I/O
O
Function
X
Tip input. Connected to the telephone line through a protection circuit
Ring input. Connected to the telephone line through a protection circuit
Input-stage amplifier gain-select output. Used to adjust the gain of the input-
stage amplifier.
Analog ground output. Internal reference voltage (V
D D
/2) output level
Ring detector input. Used for line reversal and ring signal detection.
Connected for ring detection of attenuated ring signals.
Ring detector RC terminal. Connected to an RC network which sets the ring
detector delay time.
Ring detector output. R D R C -input Schmitt-trigger buffer output. LOW -level
output when ring signal is detected.
Pow er-down control input. LOW -level for normal operation. HIGH-level for
pow er-down state. In the pow er-down state, pins AG N D , O S C O U T, D O U T,
and DV are HIGH.
Ground. Connected to the system ground potential.
Cr ystal oscillator output. The crystal oscillator element is connected between
this pin and OSCIN.
Cr ystal oscillator input. The crystal oscillator element is connected between
this pin and OSCOUT.
Test input. Tied LOW for normal operation.
FSK/DTMF discr iminator output. HIGH-level output when receiving FSK
signal, and LOW -level output when receiving DTMF signal.
Demodulator output. Demodulated FSK or DTMF signal output. HIGH-level
output in pow er-down state.
Data trigger output. Data is output on DOUT when this pin goes LOW .
Supply
1046
638
176
176
176
176
596
Y
2934
2934
2665
1954
1534
492
226
8
9
10
11
12
13
14
15
16
PDW N
GND
OSCOUT
OSCIN
IC
FSK/D T M F
DOUT
DV
VDD
I
–
O
I
I
O
O
O
–
1063
1634
2053
2634
2634
2634
2634
2211
1612
226
226
226
506
1550
1942
2623
2934
2934
NIPPON PRECISION CIRCUITS—3
SM8223A
SPECIFICATIONS
Absolute Maximum Ratings
GND = 0V
P arameter
Supply voltage range
Input voltage range
DC input current
Storage temperature range
Symbol
V
DD
V
IN
I
IN
T
stg
Rating
−0.5
to 5.0
−
0.3 to V
D D
+ 0.3
±10
−40
to 125
Unit
V
V
mA
°C
Recommended Operating Conditions
GND = 0V
Rating
P arameter
Supply voltage
Clock frequency
Clock frequency accuracy
Operating temperature
Symbol
V
DD
f
C L K
∆f
C
T
a
Condition
min
2.7
–
−0.1
−20
typ
–
3.579545
–
–
max
3.3
–
+0.1
85
V
MHz
%
°C
Unit
DC Electrical Characteristics
V
DD
= 3.0V ± 0.3V, GND = 0V, f
CLK
= 3.579545MHz, T
a
=
−20
to 85°C unless otherwise noted.
Rating
P arameter
Symbol
Condition
min
Supply current consumption
I
D D
P D W N = 0 V, RDIN = 0 V,
R D R C = 0 V, all other inputs
open
P D W N = V
D D
, RDIN = 0 V,
R D R C = 0 V, all other inputs
open
–
typ
–
max
4.5
mA
Unit
Pow er-down state current
P D WN, RDIN, R D R C LOW -level
input voltage
P D WN, RDIN, R D R C HIGH-level
input voltage
O S C I N L OW -level input voltage
OSCIN HIGH-level input voltage
D O U T, DV, R D E T, FSK/D T M F LOW -
level output current
D O U T, DV, R D E T, FSK/D T M F HIGH-
level output current
P D WN, RDIN input leakage current
R D R C output leakage current
I
D P D
–
–
15
µA
V
IL1
V
IH1
V
IL2
V
IH2
I
O L
I
O H
I
IN
I
O F F
W h e n external clock input
W h e n external clock input
–
0.7V
D D
–
0.7V
D D
2
–
−1
–
–
–
–
–
–
–
–
–
0.3V
D D
–
0.3V
D D
–
–
−0.8
1
1
V
V
V
V
mA
mA
µA
µA
NIPPON PRECISION CIRCUITS—4
SM8223A
AC Electrical Characteristics
FSK decoder
V
DD
= 3.0V ± 0.3V, GND = 0V, f
CLK
= 3.579545MHz, T
a
=
−20
to 85°C unless otherwise noted.
Rating
P arameter
Detection sensitivity
Symbol
Condition
min
Typical application circuit
M a r k signal and SPA CE
signal are same level.
Noise: Random noise from
200Hz to 3400Hz.
−40
typ
−37.5
max
0
dBm
Unit
Noise reduction ratio
20
–
–
dB
DTMF receiver
V
DD
= 3.0V ± 0.3V, GND = 0V, f
CLK
= 3.579545MHz, T
a
=
−20
to 85°C unless otherwise noted.
Rating
P arameter
Detection frequency deviation
Non-detection frequency deviation
Typical application circuit
Detection sensitivity
Non-detection sensitivity
Signal level error
High-frequency rejection ratio
Noise rejection ratio
Dial tone rejection ratio
1. Input signal is up to V
D D
level.
Typical application circuit
1
Symbol
Condition
min
±1.5% ± 2
±3.5
−32.0
–
–
–
–
–
typ
–
–
–
–
–
18
12
20
max
–
–
0.0
−50.0
6
–
–
–
Hz
%
dBm
dBm
dB
dB
dB
dB
Unit
Input-stage amplifier Characteristics
V
DD
= 3.0V ± 0.3V, GND = 0V, f
CLK
= 3.579545MHz, T
a
=
−20
to 85°C unless otherwise noted.
Rating
P arameter
Input leakage current
Input resistance
DC open-loop voltage gain
Unity gain frequency
Load capacitance
Load resistance
Symbol
I
IN
R
IN
A
VOL
f
C
C
L
R
L
Condition
min
–
–
30
80
–
50
typ
–
1
–
–
–
–
max
1
–
–
–
100
–
µA
M
Ω
dB
kHz
pF
kΩ
Unit
NIPPON PRECISION CIRCUITS—5
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
