74AUP1T57
Low-power configurable gate with voltage-level translator
Rev. 02 — 3 August 2009
Product data sheet
1. General description
The 74AUP1T57 provides low-power, low-voltage configurable logic gate functions. The
output state is determined by eight patterns of 3-bit input. The user can choose the logic
functions AND, OR, NAND, NOR, XNOR, inverter and buffer. All inputs can be connected
to V
CC
or GND.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 2.3 V to 3.6 V.
The 74AUP1T57 is designed for logic-level translation applications with input switching
levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single
2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from
3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the
entire V
CC
range.
2. Features
I
Wide supply voltage range from 2.3 V to 3.6 V
I
High noise immunity
I
ESD protection:
N
HBM JESD22-A114E Class 3A exceeds 5000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Low static power consumption; I
CC
= 1.5
µA
(maximum)
I
Latch-up performance exceeds 100 mA per JESD 78 Class II
I
Inputs accept voltages up to 3.6 V
I
Low noise overshoot and undershoot < 10 % of V
CC
I
I
OFF
circuitry provides partial Power-down mode operation
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
NXP Semiconductors
74AUP1T57
Low-power configurable gate with voltage-level translator
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AUP1T57GW
74AUP1T57GM
74AUP1T57GF
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
SC-88
XSON6
XSON6
Description
plastic surface-mounted package; 6 leads
Version
SOT363
Type number
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1
×
1.45
×
0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1
×
1
×
0.5 mm
4. Marking
Table 2.
Marking
Marking code
[1]
a7
a7
a7
Type number
74AUP1T57GW
74AUP1T57GM
74AUP1T57GF
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
3
4
B
1
Y
A
C
6
001aab583
Fig 1.
Logic symbol
74AUP1T57_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 August 2009
2 of 17
NXP Semiconductors
74AUP1T57
Low-power configurable gate with voltage-level translator
6. Pinning information
6.1 Pinning
74AUP1T57
74AUP1T57
B
GND
1
2
6
5
C
GND
V
CC
A
A
3
001aah472
B
1
6
C
B
GND
74AUP1T57
1
2
3
6
5
4
C
V
CC
Y
2
5
V
CC
3
4
Y
A
4
Y
001aah471
001aah473
Transparent top view
Transparent top view
Fig 2.
Pin configuration SOT363
(SC-88)
Fig 3.
Pin configuration SOT886
(XSON6)
Fig 4.
Pin configuration SOT891
(XSON6)
6.2 Pin description
Table 3.
Symbol
B
GND
A
Y
V
CC
C
Pin description
Pin
1
2
3
4
5
6
Description
data input
ground (0 V)
data input
data output
supply voltage
data input
7. Functional description
Table 4.
Input
C
L
L
L
L
H
H
H
H
[1]
H = HIGH voltage level;
L = LOW voltage level.
Function table
[1]
Output
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Y
H
L
H
L
L
L
H
H
74AUP1T57_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 August 2009
3 of 17
NXP Semiconductors
74AUP1T57
Low-power configurable gate with voltage-level translator
7.1 Logic configurations
Table 5.
Function selection table
Figure
see
Figure 5
see
Figure 8
see
Figure 6
and
7
see
Figure 6
and
7
see
Figure 8
see
Figure 5
see
Figure 9
see
Figure 10
see
Figure 11
Logic function
2-input AND
2-input AND with both inputs inverted
2-input NAND with inverted input
2-input OR with inverted input
2-input NOR
2-input NOR with both inputs inverted
2-input XNOR
Inverter
Buffer
V
CC
B
C
Y
B
1
2
B
C
Y
3
6
5
4
Y
B
C
Y
C
B
C
Y
B
1
2
3
6
5
4
Y
C
V
CC
001aab584
001aab585
Fig 5.
2-input AND gate or 2-input NOR gate with
both inputs inverted
Fig 6.
2-input NAND gate with input B inverted or
2-input OR gate with inverted C input
V
CC
V
CC
A
C
Y
1
2
A
C
Y
A
3
6
5
4
Y
A
C
Y
A
C
A
C
Y
1
2
3
6
5
4
Y
C
001aab586
001aab587
Fig 7.
2-input NAND gate with input C inverted or
2-input OR gate with inverted A input
Fig 8.
2-input NOR gate or 2-input AND gate with
both inputs inverted
V
CC
V
CC
B
B
C
Y
1
2
3
6
5
4
Y
C
A
Y
A
1
2
3
6
5
4
Y
001aab588
001aab589
Fig 9.
2-input XNOR gate
Fig 10. Inverter
74AUP1T57_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 August 2009
4 of 17
NXP Semiconductors
74AUP1T57
Low-power configurable gate with voltage-level translator
V
CC
B
B
Y
1
2
3
6
5
4
Y
001aab590
Fig 11. Buffer
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
−0.5
−50
−0.5
−50
[1]
Max
+4.6
-
+4.6
-
+4.6
±20
50
-
+150
250
Unit
V
mA
V
mA
V
mA
mA
mA
°C
mW
V
O
< 0 V
Active mode and Power-down mode
V
O
= 0 V to V
CC
−0.5
-
-
−50
−65
T
amb
=
−40 °C
to +125
°C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SC-88 package: above 87.5
°C
the value of P
tot
derates linearly with 4.0 mW/K.
For XSON6 packages: above 118
°C
the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 7.
Symbol
V
CC
V
I
V
O
T
amb
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
2.3
0
0
0
−40
Max
3.6
3.6
V
CC
3.6
+125
Unit
V
V
V
V
°C
74AUP1T57_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 August 2009
5 of 17
嵌入式系统
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