74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Rev. 03 — 27 April 2010
Product data sheet
1. General description
The 74ALVCH16374 is 16-bit edge-triggered flip-flop featuring separate D-type inputs for
each flip-flop and 3-state outputs for bus oriented applications.
Incorporates bus hold data inputs which eliminate the need for external pull-up or
pull-down resistors to hold unused inputs.
The 74ALVCH16374 consists of 2 sections of eight edge-triggered flip-flops. A clock (CP)
input and an output enable (OE) are provided per 8-bit section.
The flip-flops will store the state of their individual D-inputs that meet the set-up and hold
time requirements on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the flip-flops are available at the outputs. When OE is
HIGH, the outputs go the high-impedance OFF-state. Operation of the OE input does not
affect the state of the flip-flops.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standard JESD8-B
CMOS low power consumption
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple V
CC
and GND pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold
Output drive capability 50
Ω
transmission lines at 85
°C
Current drive
±24
mA at V
CC
= 3.0 V
NXP Semiconductors
74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
3. Ordering information
Table 1.
Ordering information
Temperature range
−40 °C
to +85
°C
−40 °C
to +85
°C
Package
Name
74ALVCH16374DL
74LVCH16374DGG
SSOP48
TSSOP48
Description
plastic shrink small outline package; 48 leads;
body width 7.5 mm
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
Version
SOT370-1
SOT362-1
Type number
4. Functional diagram
1
1OE
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1CP
48
2CP
25
001aal770
24
2OE
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
Fig 1.
Logic symbol
74ALVCH16374_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2010
2 of 17
NXP Semiconductors
74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
1OE
1CP
2OE
2CP
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1EN
C1
2EN
C2
1D
1
2
3
5
6
8
9
11
12
2D
2
13
14
16
17
19
20
22
23
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
001aal772
Fig 2.
IEC logic symbol
V
CC
data input
to internal circuit
mna705
Fig 3.
Bus hold circuit
1D0
D
CP
Q
1Q0
2D0
D
CP
Q
2Q0
FF1
1CP
2CP
FF9
1OE
2OE
to 7 other channels
to 7 other channels
001aal771
Fig 4.
Logic diagram
74ALVCH16374_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2010
3 of 17
NXP Semiconductors
74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
5. Pinning information
5.1 Pinning
74ALVCH16374
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1
2
3
4
5
6
7
8
9
48 1CP
47 1D0
46 1D1
45 GND
44 1D2
43 1D3
42 V
CC
41 1D4
40 1D5
39 GND
38 1D6
37 1D7
36 2D0
35 2D1
34 GND
33 2D2
32 2D3
31 V
CC
30 2D4
29 2D5
28 GND
27 2D6
26 2D7
25 2CP
001aal769
GND 10
1Q6 11
1Q7 12
2Q0 13
2Q1 14
GND 15
2Q2 16
2Q3 17
V
CC
18
2Q4 19
2Q5 20
GND 21
2Q6 22
2Q7 23
2OE 24
Fig 5.
Pin configuration
74ALVCH16374_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2010
4 of 17
NXP Semiconductors
74ALVCH16374
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
5.2 Pin description
Table 2.
Symbol
1OE, 2OE
1Q0 to 1Q7
2Q0 to 2Q7
GND
V
CC
1D0 to 1D7
2D0 to 2D7
1CP, 2CP
Pin description
Pin
1, 24
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20, 22, 23
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
47, 46, 44, 43, 41, 40, 38, 37
36, 35, 33, 32, 30, 29, 27, 26
48, 25
Description
output enable input (active LOW)
3-state flip-flop outputs
3-state flip-flop outputs
ground (0 V)
positive supply voltage
data inputs
data inputs
clock input
6. Functional description
6.1 Function table
Table 3.
Inputs
nOE
L
L
H
H
[1]
Function table
[1]
nCP
↑
↑
↑
↑
Dn
l
h
l
h
Internal
flip-flops
L
H
L
H
Outputs Q0 to Q7
L
H
Z
Z
load register and disable outputs
Operating mode
load and read register
H = HIGH voltage level;
L = LOW voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
↑
= LOW-to-HIGH clock transition;
Z = high-impedance OFF-state.
74ALVCH16374_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 27 April 2010
5 of 17
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