74ALVC32
Quad 2-input OR gate
Rev. 02 — 10 December 2007
Product data sheet
1. General description
The 74ALVC32 is a quad 2-input OR gate.
Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.
2. Features
s
s
s
s
s
s
s
Wide supply voltage range from 1.65 V to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standards:
x
JESD8-7 (1.65 V to 1.95 V)
x
JESD8-5 (2.3 V to 2.7 V)
x
JESD8B/JESD36 (2.7 V to 3.6 V)
s
ESD protection:
x
HBM JESD22-A114E exceeds 2000 V
x
MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74ALVC32D
74ALVC32PW
74ALVC32BQ
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
SO14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
SOT762-1
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
NXP Semiconductors
74ALVC32
Quad 2-input OR gate
4. Functional diagram
1
2
≥1
3
4
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
1Y
3
5
≥1
6
2Y
6
9
10
≥1
8
3Y
8
12
13
4Y
11
≥1
11
mna242
mna243
Fig 1. Logic symbol
Fig 2. IEC logic symbol
A
Y
B
mna241
Fig 3. Logic diagram (one gate)
5. Pinning information
5.1 Pinning
terminal 1
index area
1B
1Y
2A
2B
2B
2Y
GND
5
6
7
001aad101
1A
1B
1Y
2A
1
2
3
4
14 V
CC
13 4B
12 4A
2
3
4
5
6
7
GND
3Y
8
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
3A
32
11 4Y
10 3B
9
8
3A
3Y
GND
(1)
2Y
1
1A
32
001aad102
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration SO14 and TSSOP14
Fig 5. Pin configuration DHVQFN14
74ALVC32_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 10 December 2007
2 of 13
NXP Semiconductors
74ALVC32
Quad 2-input OR gate
5.2 Pin description
Table 2.
Symbol
nA
nB
nY
V
CC
GND
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
14
7
Description
data input
data input
data output
supply voltage
ground (0 V)
6. Functional description
Table 3.
Input nA
L
L
H
H
[1]
H = HIGH voltage level
L = LOW voltage level
Function table
[1]
Input nB
L
H
L
H
Output nY
L
H
H
H
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
V
O
> V
CC
or V
O
< 0 V
output HIGH or LOW state
output 3-state
power-down mode, V
CC
= 0 V
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
[2]
[1] [2]
Conditions
V
I
< 0 V
Min
−0.5
−50
−0.5
-
−0.5
−0.5
−0.5
-
-
−100
−65
Max
+4.6
-
+4.6
±50
V
CC
+ 0.5
+4.6
+4.6
±50
100
-
+150
500
Unit
V
mA
V
mA
V
V
V
mA
mA
mA
°C
mW
output current
supply current
ground current
storage temperature
total power dissipation
V
O
= 0 V to V
CC
T
amb
=
−40 °C
to +85
°C
[3]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (power-down mode), the output voltage can be 3.6 V in normal operation.
For SO14 packages: above 70
°C
derate linearly with 8 mW/K.
For TSSOP14 packages: above 60
°C
derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
°C
derate linearly with 4.5 mW/K.
74ALVC32_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 10 December 2007
3 of 13
NXP Semiconductors
74ALVC32
Quad 2-input OR gate
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
output HIGH or LOW state
output 3-state
power-down mode; V
CC
= 0 V
T
amb
∆t/∆V
ambient temperature
input transition rise and fall rate
in free air
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
Conditions
Min
1.65
0
0
0
0
−40
0
0
Max
3.6
3.6
V
CC
3.6
3.6
+85
20
10
Unit
V
V
V
V
V
°C
ns/V
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level input voltage
Conditions
Min
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
IL
LOW-level input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
−100 µA;
V
CC
= 1.65 V to 3.6 V
I
O
=
−6
mA; V
CC
= 1.65 V
I
O
=
−12
mA; V
CC
= 2.3 V
I
O
=
−18
mA; V
CC
= 2.3 V
I
O
=
−12
mA; V
CC
= 2.7 V
I
O
=
−18
mA; V
CC
= 3.0 V
I
O
=
−24
mA; V
CC
= 3.0 V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 100
µA;
V
CC
= 1.65 V to 3.6 V
I
O
= 6 mA; V
CC
= 1.65 V
I
O
= 12 mA; V
CC
= 2.3 V
I
O
= 18 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 18 mA; V
CC
= 3.0 V
I
O
= 24 mA; V
CC
= 3.0 V
I
I
I
OFF
74ALVC32_2
−40 °C
to +85
°C
Typ
[1]
-
-
-
-
-
-
-
1.51
2.10
2.01
2.53
2.76
2.68
-
0.11
0.17
0.25
0.16
0.23
0.30
±0.1
±0.1
Max
-
-
-
0.7
0.8
-
-
-
-
-
-
-
0.2
0.3
0.4
0.6
0.4
0.4
0.55
±5
±10
0.65
×
V
CC
1.7
2.0
-
-
-
V
CC
−
0.2
1.25
1.8
1.7
2.2
2.4
2.2
-
-
-
-
-
-
-
-
-
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
0.35
×
V
CC
V
input leakage current
power-off leakage current
V
CC
= 3.6 V; V
I
= 3.6 V or GND
V
CC
= 0 V; V
I
or V
O
= 0 V to 3.6 V
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 10 December 2007
4 of 13
NXP Semiconductors
74ALVC32
Quad 2-input OR gate
Table 6.
Static characteristics
…continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
I
CC
∆I
CC
C
I
[1]
Conditions
Min
V
CC
= 3.6 V; V
I
= V
CC
or GND;
I
O
= 0 A
per input pin; V
CC
= 3.0 V to 3.6 V;
V
I
= V
CC
−
0.6 V; I
O
= 0 A
-
-
-
−40 °C
to +85
°C
Typ
[1]
0.2
5
3.5
Max
10
750
-
Unit
µA
µA
pF
supply current
additional supply current
input capacitance
All typical values are measured at V
CC
= 3.3 V (unless stated otherwise) and T
amb
= 25
°C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see
Figure 7.
Symbol
t
pd
Parameter
propagation delay
Conditions
CP to Qn; see
Figure 6
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
C
PD
power dissipation
capacitance
per gate; V
I
= GND to V
CC
; V
CC
= 3.3 V
[3]
[2]
−40 °C
to +85
°C
Min
1.0
1.0
1.0
1.0
-
Typ
[1]
2.8
2.0
2.2
2.0
25
Max
4.7
3.1
2.9
2.8
-
Unit
ns
ns
ns
ns
pF
[1]
[2]
[3]
Typical values are measured at T
amb
= 25
°C
t
pd
is the same as t
PHL
and t
PLH
.
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volts
N = number of inputs switching
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs
74ALVC32_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 10 December 2007
5 of 13
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