Includes
FLEX 10KA
FLEX 10K
Embedded Programmable
Logic Device Family
Data Sheet
®
January 2003, ver. 4.2
Features...
■
■
■
The industry’s first embedded programmable logic device (PLD)
family, providing System-on-a-Programmable-Chip (SOPC)
integration
–
Embedded array for implementing megafunctions, such as
efficient memory and specialized logic functions
–
Logic array for general logic functions
High density
–
10,000 to 250,000 typical gates (see
Tables 1
and
2)
–
Up to 40,960 RAM bits; 2,048 bits per embedded array block
(EAB), all of which can be used without reducing logic capacity
System-level features
–
MultiVolt
TM
I/O interface support
–
5.0-V tolerant input pins in FLEX
®
10KA devices
–
Low power consumption (typical specification less than 0.5 mA
in standby mode for most devices)
–
FLEX 10K and FLEX 10KA devices support peripheral
component interconnect Special Interest Group (PCI SIG)
PCI
Local Bus Specification, Revision 2.2
–
FLEX 10KA devices include pull-up clamping diode, selectable
on a pin-by-pin basis for 3.3-V PCI compliance
–
Select FLEX 10KA devices support 5.0-V PCI buses with eight or
fewer loads
–
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming any device logic
Table 1. FLEX 10K Device Features
Feature
Typical gates (logic and RAM)
(1)
Maximum system gates
Logic elements (LEs)
Logic array blocks (LABs)
Embedded array blocks (EABs)
Total RAM bits
Maximum user I/O pins
EPF10K10
EPF10K10A
10,000
31,000
576
72
3
6,144
150
EPF10K20
20,000
63,000
1,152
144
6
12,288
189
EPF10K30
EPF10K30A
30,000
69,000
1,728
216
6
12,288
246
EPF10K40
40,000
93,000
2,304
288
8
16,384
189
EPF10K50
EPF10K50V
50,000
116,000
2,880
360
10
20,480
310
Altera Corporation
DS-F10K-4.2
1
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Table 2. FLEX 10K Device Features
Feature
Typical gates (logic and
RAM)
(1)
Maximum system gates
LEs
LABs
EABs
Total RAM bits
Maximum user I/O pins
Note to tables:
(1)
The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum
system gates.
EPF10K70
70,000
118,000
3,744
468
9
18,432
358
EPF10K100
EPF10K100A
100,000
158,000
4,992
624
12
24,576
406
EPF10K130V
130,000
211,000
6,656
832
16
32,768
470
EPF10K250A
250,000
310,000
12,160
1,520
20
40,960
470
...and More
Features
–
–
–
–
–
Devices are fabricated on advanced processes and operate with
a 3.3-V or 5.0-V supply voltage (see
Table 3
In-circuit reconfigurability (ICR) via external configuration
device, intelligent controller, or JTAG port
ClockLock
TM
and ClockBoost
TM
options for reduced clock
delay/skew and clock multiplication
Built-in low-skew clock distribution trees
100% functional testing of all devices; test vectors or scan chains
are not required
Table 3. Supply Voltages for FLEX 10K & FLEX 10KA Devices
5.0-V Devices
EPF10K10
EPF10K20
EPF10K30
EPF10K40
EPF10K50
EPF10K70
EPF10K100
3.3-V Devices
EPF10K10A
EPF10K30A
EPF10K50V
EPF10K100A
EPF10K130V
EPF10K250A
2
Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
■
■
■
■
■
■
Flexible interconnect
–
FastTrack
®
Interconnect continuous routing structure for fast,
predictable interconnect delays
–
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
–
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
–
Tri-state emulation that implements internal tri-state buses
–
Up to six global clock signals and four global clear signals
Powerful I/O pins
–
Individual tri-state output enable control for each pin
–
Open-drain option on each I/O pin
–
Programmable output slew-rate control to reduce switching
noise
–
FLEX 10KA devices support hot-socketing
Peripheral register for fast setup and clock-to-output delay
Flexible package options
–
Available in a variety of packages with 84 to 600 pins (see
Tables 4
and
5)
–
Pin-compatibility with other FLEX 10K devices in the same
package
–
FineLine BGA
TM
packages maximize board space efficiency
Software design support and automatic place-and-route provided by
Altera development systems for Windows-based PCs and Sun
SPARCstation, HP 9000 Series 700/800 workstations
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
DesignWare components, Verilog HDL, VHDL, and other interfaces
to popular EDA tools from manufacturers such as Cadence,
Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity,
VeriBest, and Viewlogic
Altera Corporation
3
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Table 4. FLEX 10K Package Options & I/O Pin Count
Device
84-Pin
PLCC
59
66
Note (1)
144-Pin TQFP
208-Pin
PQFP
RQFP
134
134
147
147
102
147
147
189
189
189
189
189
189
189
189
100-Pin
TQFP
240-Pin
PQFP
RQFP
EPF10K10
EPF10K10A
EPF10K20
EPF10K30
EPF10K30A
EPF10K40
EPF10K50
EPF10K50V
EPF10K70
EPF10K100
EPF10K100A
EPF10K130V
EPF10K250A
102
102
102
Table 5. FLEX 10K Package Options & I/O Pin Count (Continued)
Device
EPF10K10
EPF10K10A
EPF10K20
EPF10K30
EPF10K30A
EPF10K40
EPF10K50
EPF10K50V
EPF10K70
EPF10K100
EPF10K100A
EPF10K130V
EPF10K250A
470
470
358
406
274
274
274
191
246
246
150
Note (1)
484-Pin
FineLine BGA
150
(2)
503-Pin 599-Pin
PGA
PGA
256-Pin
FineLine BGA
356-Pin
BGA
600-Pin
BGA
403-Pin
PGA
246
310
369
406
470
470
4
Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
FLEX 10K and FLEX 10KA device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), pin-grid array (PGA),
and FineLine BGA
TM
packages.
This option is supported with a 256-pin FineLine BGA package. By using SameFrame pin migration, all FineLine
BGA packages are pin compatible. For example, a board can be designed to support both 256-pin and 484-pin
FineLine BGA packages. The Altera software automatically avoids conflicting pins when future migration is set.
(2)
General
Description
Altera’s FLEX 10K devices are the industry’s first embedded PLDs. Based
on reconfigurable CMOS SRAM elements, the Flexible Logic Element
MatriX (FLEX) architecture incorporates all features necessary to
implement common gate array megafunctions. With up to 250,000 gates,
the FLEX 10K family provides the density, speed, and features to integrate
entire systems, including multiple 32-bit buses, into a single device.
FLEX 10K devices are reconfigurable, which allows 100% testing prior to
shipment. As a result, the designer is not required to generate test vectors
for fault coverage purposes. Additionally, the designer does not need to
manage inventories of different ASIC designs; FLEX 10K devices can be
configured on the board for the specific functionality required.
Table 6
shows FLEX 10K performance for some common designs. All
performance values were obtained with Synopsys DesignWare or LPM
functions. No special design technique was required to implement the
applications; the designer simply inferred or instantiated a function in a
Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or
schematic design file.
Table 6. FLEX 10K & FLEX 10KA Performance
Application
Resources
Used
LEs
16-bit loadable
counter
(1)
16-bit accumulator
(1)
16-to-1 multiplexer
(2)
256
×
8 RAM read
cycle speed
(3)
256
×
8 RAM write
cycle speed
(3)
Notes:
(1)
(2)
(3)
The speed grade of this application is limited because of clock high and low specifications.
This application uses combinatorial inputs and outputs.
This application uses registered inputs and outputs.
Performance
-1 Speed
Grade
204
204
4.2
172
106
Units
-4 Speed
Grade
95
95
7.0
84
63
MHz
MHz
ns
MHz
MHz
EABs
0
0
0
1
1
-2 Speed
Grade
166
166
5.8
145
89
-3 Speed
Grade
125
125
6.0
108
68
16
16
10
0
0
Altera Corporation
5
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