128K X 36, 256K X 18, 3.3V
SYNCHRONOUS SRAMS WITH
2.5V I/O OPTION, PIPELINED OUTPUTS,
BURST COUNTER,
SINGLE CYCLE DESELECT
PRELIMINARY
IDT71V2576
IDT71V2578
IDT71V3576
IDT71V3578
FEATURES:
• 128K x 36, 256K x 18 memory configurations
• Supports high system speed:
– 200MHz 3.1ns clock access time
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
•
LBO
input selects interleaved or linear burst mode
• Self-timed write cycle with global write control (GW byte write
GW),
GW
enable (BWE and byte writes (BW
BWE),
BWx)
BWE
BW
• 3.3V core power supply
• Power down controlled by ZZ input
• 2.5V or 3.3V I/O option
• Packaged in a JEDEC Standard 100-lead plastic thin quad flatpack
(TQFP) and 119-lead ball grid array (BGA)
DESCRIPTION:
The IDT71Vx576/578 are high-speed SRAMs organized as 128K x 36/
256K x 18. The IDT71Vx576/578 SRAMs contain write, data, address and
control registers. Internal logic allows the SRAM to generate a self-timed write
based upon a decision which can be left until the end of the write cycle.
The burst mode feature offers the highest level of performance to the system
designer, as the IDT71Vx576/578 can provide four cycles of data for a single
address presented to the SRAM. An internal burst address counter accepts the
first cycle address from the processor, initiating the access sequence. The first
cycle of output data will be pipelined for one cycle before it is available on the
next rising clock edge. If burst mode operation is selected (ADV=LOW),
the subsequent three cycles of output data will be available to the user on
the next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the
LBO
input pin.
The IDT71Vx576/578 SRAMs utilize IDT’s latest high-performance CMOS
process and are packaged in a JEDEC standard 14mm x 20mm 100-lead thin
plastic quad flatpack (TQFP) as well as a 119-lead ball grid array (BGA).
PIN DESCRIPTION SUMMARY
A
0
-A
17
CE
CS
0
,
CS
1
OE
GW
BWE
BW
1
,
BW
2
,
BW
3
,
BW
4
(1)
CLK
ADV
ADSC
ADSP
LBO
ZZ
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
V
DD
, V
DDQ
V
SS
Ad d re ss Inp uts
Chip Enab le
Chip Se le cts
Outp ut Enab le
Glo b al Write Enab le
Byte Write Enab le
Ind ivid ual Byte Write Se le cts
Clo ck
Burst Ad d re ss Ad vance
Ad d re ss Status (Cache Co ntro lle r)
Ad d re ss Status (Pro ce sso r)
Line ar / Inte rle ave d Burst Ord e r
S le e p Mo d e
Data Inp ut / Outp ut
Co re Po we r, I/O Po we r
Gro und
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
I/O
Sup p ly
Sup p ly
Synchro no us
Synchro no us
Synchro no us
Asynchro no us
Synchro no us
Synchro no us
Synchro no us
N/A
Synchro no us
Synchro no us
Synchro no us
DC
Asynchro no us
Synchro no us
N/A
N/A
4876 tb l 01
NOTE:
1.
BW
3
and
BW
4
are not applicable for the IDT71Vx578.
APRIL 1999
1
©
1998
Integrated Device Technology, Inc.
DSC-4876/2
IDT71Vx576/IDTVx578
COMMERCIAL TEMPERATURE RANGE
PIN DEFINITIONS
(1)
Symbol
A
0
-A
17
ADSC
ADSP
ADV
Pin Function
Ad d re ss Inp uts
Ad d re ss Status
(Cache Co ntro lle r)
Ad d re ss Status
(Pro ce sso r)
Burst Ad d re ss
Ad vance
Byte Write Enab le
I/O
I
I
I
I
Active
N/A
LOW
LOW
LOW
Description
Synchro no us Ad d re ss inp uts. The ad d re ss re g iste r is trig g e re d b y a co mb inatio n o f the
rising e d g e o f CLK and
ADSC
Lo w o r
ADSP
Lo w and
CE
Lo w.
Synchro no us Ad d re ss Status fro m Cache Co ntro lle r.
ADSC
is an active LOW inp ut that is
use d to lo ad the ad d re ss re g iste rs with ne w ad d re sse s.
Synchro no us Ad d re ss Status fro m Pro ce sso r.
ADSP
is an active LOW inp ut that is use d to
lo ad the ad d re ss re g iste rs with ne w ad d re sse s.
ADSP
is g ate d b y
CE
.
Synchro no us Ad d re ss Ad vance .
ADV
is an active LOW inp ut that is use d to ad vance the
inte rnal b urst co unte r, co ntro lling b urst acce ss afte r the initial ad d re ss is lo ad e d . Whe n the
inp ut is HIGH the b urst co unte r is no t incre me nte d ; that is, the re is no ad d re ss ad vance .
Synchro no us b yte write e nab le g ate s the b yte write inp uts
BW
1
-
BW
4
. If
BWE
is LOW at the
rising e d g e o f CLK the n
BW
x inp uts are p asse d to the ne xt stag e in the circuit. If
BWE
is
HIGH the n the b yte write inp uts are b lo cke d and o nly
GW
can initiate a write cycle .
Synchro no us b yte write e nab le s.
BW
1
co ntro ls I/O
0-7
, I/O
P1
,
BW
2
co ntro ls I/O
8-15
, I/O
P2
, e tc.
Any active b yte write cause s all o utp uts to b e d isab le d .
Synchro no us chip e nab le .
CE
is use d with CS
0
and
CS
1
to e nab le the IDT71Vx576/578.
CE
also g ate s
ADSP
.
This is the clo ck inp ut. All timing re fe re nce s fo r the d e vice are mad e with re sp e ct to this
inp ut.
Synchro no us active HIGH chip se le ct. CS
0
is use d with
CE
and
CS
1
to e nab le the chip .
Synchro no us active LOW chip se le ct.
CS
1
is use d with
CE
and CS
0
to e nab le the chip .
Synchro no us g lo b al write e nab le . This inp ut will write all fo ur 9-b it d ata b yte s whe n LOW
o n the rising e d g e o f CLK.
GW
sup e rse d e s ind ivid ual b yte write e nab le s.
Synchro no us d ata inp ut/o utp ut (I/O) p ins. Bo th the d ata inp ut p ath and d ata o utp ut p ath are
re g iste re d and trig g e re d b y the rising e d g e o f CLK.
Asynchro no us b urst o rd e r se le ctio n inp ut. Whe n
LBO
is HIGH, the inte rle ave d b urst
se q ue nce is se le cte d . Whe n
LBO
is LOW the Line ar b urst se q ue nce is se le cte d .
LBO
is a
static inp ut and must no t chang e state while the d e vice is o p e rating .
Asynchro no us o utp ut e nab le . Whe n
OE
is LOW the d ata o utp ut d rive rs are e nab le d o n the
I/O p ins if the chip is also se le cte d . Whe n
OE
is HIGH the I/O p ins are in a hig h-
imp e d ance state .
3.3V co re p o we r sup p ly.
3.3V o r 2.5V I/O Sup p ly.
Gro und .
NC p ins are no t e le ctrically co nne cte d to the d e vice .
Asynchro no us sle e p mo d e inp ut. ZZ HIGH will g ate the CLK inte rnally and p o we r d o wn the
IDT71Vx576/78 to its lo we st p o we r co nsump tio n le ve l. Data re te ntio n is g uarante e d in
S le e p Mo d e .
4876 tb l 02
BWE
I
LOW
BW
1
-
BW
4
CE
CLK
CS
0
CS
1
GW
I/O
0
-I/O
31
I/O
P1
-I/O
P4
LBO
Ind ivid ual Byte
Write Enab le s
Chip Enab le
Clo ck
Chip Se le ct 0
Chip Se le ct 1
Glo b al Write
Enab le
Data Inp ut/Outp ut
Line ar Burst Ord e r
I
I
I
I
I
I
I/O
I
LOW
LOW
N/A
HIGH
LOW
LOW
N/A
LOW
OE
Outp ut Enab le
I
LOW
V
DD
V
DDQ
V
SS
NC
ZZ
Po we r Sup p ly
Po we r Sup p ly
Gro und
No Co nne ct
S le e p Mo d e
N/A
N/A
N/A
N/A
I
N/A
N/A
N/A
N/A
HIGH
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
2
©
1998
Integrated Device Technology, Inc.
DSC-4876/2
IDT71Vx576/IDTVx578
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
LBO
ADV
CE#
Burst
Sequence
INTERNAL
ADDRESS
CLK
ADSC
ADSP
CE#
Binary
Counter
CLR#
2
Burst
Logic
17/18
A0*
A1*
Q0
Q1
128K x 36/
256K x 18-
BIT
MEMORY
ARRAY
2
A
0
,A
1
17/18
A
2
ÐA
17
36/18
36/18
A
0
ÐA
16/17
GW
BWE
BW
1
ADDRESS
REGISTER
Byte 1
Write Register
Byte 1
Write Driver
9
Byte 2
Write Register
Byte 2
Write Driver
BW
2
Byte 3
Write Register
9
Byte 3
Write Driver
BW
3
Byte 4
Write Register
9
Byte 4
Write Driver
BW
4
9
OUTPUT
REGISTER
CE
CS
0
CS
1
D
Q
Enable
Register
CE#
DATA
INPUT
REGISTER
ZZ
Powerdown
D
Q
Enable
Delay
Register
OE
OUTPUT
BUFFER
OE
I/O
0
— I/O
31
I/O
P1
— I/O
P4
36/18
4876 drw 01
3
©
1998
Integrated Device Technology, Inc.
DSC-4876/2
IDT71Vx576/IDTVx578
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
V
TERM
(3,6)
V
TERM
(4,6)
Rating
Te rminal Vo ltag e with
Re s p e c t to GND
Te rminal Vo ltag e with
Re s p e c t to GND
Te rminal Vo ltag e with
Re s p e c t to GND
Te rminal Vo ltag e with
Re s p e c t to GND
Op e rating Te mp e rature
Commercial
-0.5 to +4.6
-0.5 to V
DD
-0.5 to V
DD
+0.5
-0.5 to V
DDQ
+0.5
-0 to +70
Unit
V
V
V
V
o
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY
VOLTAGE
Grade
Co mme rc ial
Co mme rc ial
Temperature
0° C to +70° C
0° C to +70° C
V
SS
0V
0V
V
DD
3.3V± 5%
3.3V± 5%
V
DDQ
2.5V± 5%
V
DD
4876 tb l 04
V
TERM
(5,6)
T
A
T
BIAS
T
STG
P
T
I
OUT
RECOMMENDED DC OPERATING
CONDITIONS WITH VDDQ AT 2.5V
Symbol
V
DD
V
DDQ
Parameter
Co re Sup p ly Vo ltag e
I/O Sup p ly Vo ltag e
Sup p ly Vo ltag e
Inp ut Hig h Vo ltag e - Inp uts
V
IH
V
IL
Inp ut Hig h Vo ltag e - I/O
Inp ut Lo w Vo ltag e
1.7
-0.3
(2)
____
C
C
C
Min.
3.135
2.375
0
1.7
Typ.
3.3
2.5
0
____
Max.
3.465
2.625
0
V
DD
+0.3
V
DDQ
+0.3
(1)
0.7
Unit
V
V
V
V
V
V
4876 tb l 05
Te mp e rature
Und e r Bias
Sto rag e
Te mp e rature
Po we r Dis s ip atio n
DC Outp ut Curre nt
-55 to +125
-55 to +125
1.25
50
o
o
V
SS
V
IH
W
mA
4876 tb l 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
DD
terminals only.
3. V
DDQ
terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have ramped up.
Power supply sequencing is not necessary; however, the voltage on any input or I/O pin
cannot exceed V
DDQ
during power supply ramp up.
____
NOTES:
1. V
IH
(max) = V
DDQ
+ 1.0V for pulse width less than t
CYC/2
, once per cycle.
2. V
IL
(min) = -1.0V for pulse width less than t
CYC/2
, once per cycle.
RECOMMENDED DC OPERATING
CONDITIONS WITH VDDQ AT 3.3V
Symbol
V
DD
V
DDQ
Parameter
Co re Sup p ly Vo ltag e
I/O Sup p ly Vo ltag e
Sup p ly Vo ltag e
Inp ut Hig h Vo ltag e - Inp uts
Min.
3.135
3.135
0
2.0
Inp ut Hig h Vo ltag e - I/O
Inp ut Lo w Vo ltag e
2.0
-0.3
(2)
Typ.
3.3
3.3
0
____
Max.
3.465
3.465
0
V
DD
+0.3
Unit
V
V
V
V
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
I/O
Parameter
(1)
Inp ut Cap ac itanc e
I/O Cap ac itanc e
Conditions
V
IN
= 3d V
V
OUT
= 3d V
Max.
5
7
Unit
pF
pF
V
SS
V
IH
V
IH
V
IL
____
V
DDQ
+0.3
(1)
0.8
V
V
4876 tb l 06
____
4876 tb l 07
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
NOTES:
1. V
IH
(max) = V
DDQ
+ 1.0V for pulse width less than t
CYC/2
, once per cycle.
2. V
IL
(min) = -1.0V for pulse width less than t
CYC/2
, once per cycle.
4
©
1998
Integrated Device Technology, Inc.
DSC-4876/2
IDT71Vx576/IDTVx578
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION 128K x 36 TQFP
BW
3
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
A
6
A
7
CE
CS
0
BW
4
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/O
P3
I/O
16
I/O
17
V
DDQ
V
SS
I/O
18
I/O
19
I/O
20
I/O
21
V
SS
V
DDQ
I/O
22
I/O
23
V
DD
(1)
V
DD
NC
V
SS
I/O
24
I/O
25
V
DDQ
V
SS
I/O
26
I/O
27
I/O
28
I/O
29
V
SS
V
DDQ
I/O
30
I/O
31
I/O
P4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
P2
I/O
15
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
NC
V
DD
ZZ
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
I/O
P1
4876 drw 02
LBO
A
5
A
4
A
3
A
2
A
1
A
0
NC
(2)
NC
(2)
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
15
TOP VIEW
NOTES:
1. Pins 14 does not have to be directly connected to V
DD
as long as the input voltage is
≥
V
IH
.
2. Pins 38 and 39 can be either NC or connected to V
SS.
5
©
1998
Integrated Device Technology, Inc.
DSC-4876/2
A
16
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