74ABT16240A
16-bit inverting buffer/line driver; 3-state
Rev. 04 — 25 March 2009
Product data sheet
1. General description
The 74ABT16240A high-performance Bipolar CMOS (BiCMOS) device combines low
static and dynamic power dissipation with high speed and high output drive.
The 74ABT16240A is an inverting 16-bit buffer that is ideal for driving bus lines. The
device features four output enable inputs (1OE, 2OE, 3OE, 4OE), each controlling four of
the 3-state outputs.
2. Features
I
I
I
I
I
I
I
I
I
I
16-bit bus interface
Multiple V
CC
and GND pins minimize switching noise
Power-up 3-state
3-state buffers
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Output capability: +64 mA and
−32
mA
Live insertion and extraction permitted
Latch-up performance: JESD 78 Class II
ESD protection:
N
MIL STD 883 method 3015: exceeds 2000 V
N
CDM JESD 22-C101-C exceeds 1000 V
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74ABT16240ADGG
74ABT16240ADL
−40 °C
to +85
°C
−40 °C
to +85
°C
TSSOP48
SSOP48
Description
plastic thin shrink small outline package; 48 leads;
body width 6.1 mm
Version
SOT362-1
Type number
plastic shrink small outline package; 48 leads; body SOT370-1
width 7.5 mm
NXP Semiconductors
74ABT16240A
16-bit inverting buffer/line driver; 3-state
4. Functional diagram
1
1OE
48
2OE
25
3OE
24
4OE
1A0
1A1
43
1A3
1OE
1Y3
6
32
3A3
3OE
3Y3
17
1A2
1A3
1
25
2Y0
2A0
2A1
41
40
2A0
8
9
30
29
4A0
4Y0
19
20
2A2
2A3
3A0
3A1
3A2
22
3A3
4A0
23
4A1
4A2
48
2OE
24
4OE
001aad261
47
46
1A0
1Y0
2
3
36
35
3A0
3Y0
13
14
1A1
1Y1
3A1
3Y1
EN1
EN2
EN3
EN4
1
1
2
3
5
6
1
2
8
9
11
12
1
3
13
14
16
17
1
4
19
20
22
23
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
3Y0
3Y1
3Y2
3Y3
4Y0
4Y1
4Y2
4Y3
44
1A2
1Y2
5
33
3A2
3Y2
16
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2A1
2Y1
4A1
4Y1
38
2A2
2Y2
11
27
4A2
4Y2
37
2A3
2Y3
12
26
4A3
4Y3
4A3
001aad262
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74ABT16240A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 March 2009
2 of 14
NXP Semiconductors
74ABT16240A
16-bit inverting buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
1OE
1Y0
1Y1
GND
1Y2
1Y3
V
CC
2Y0
2Y1
1
2
3
4
5
6
7
8
9
48 2OE
47 1A0
46 1A1
45 GND
44 1A2
43 1A3
42 V
CC
41 2A0
40 2A1
39 GND
38 2A2
37 2A3
36 3A0
35 3A1
34 GND
33 3A2
32 3A3
31 V
CC
30 4A0
29 4A1
28 GND
27 4A2
26 4A3
25 3OE
001aaj891
GND 10
2Y2 11
2Y3 12
3Y0 13
3Y1 14
GND 15
3Y2 16
3Y3 17
V
CC
18
4Y0 19
4Y1 20
GND 21
4Y2 22
4Y3 23
4OE 24
74ABT16240A
Fig 3. Pin configuration
74ABT16240A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 March 2009
3 of 14
NXP Semiconductors
74ABT16240A
16-bit inverting buffer/line driver; 3-state
5.2 Pin description
Table 2.
Symbol
1OE
1Y[0:3]
GND
V
CC
2Y[0:3]
GND
3Y[0:3]
GND
V
CC
4Y[0:3]
GND
4OE
3OE
GND
4A[0:3]
V
CC
GND
3A[0:3]
GND
2A[0:3]
V
CC
GND
1A[0:3]
2OE
Pin description
Pin
1
2, 3, 5, 6
4
7
8, 9, 11, 12
10
15
18
21
24
25
28
31
34
39
42
45
48
Description
1 output enable (LOW active)
1 data output 0 to output 3
ground (0 V)
supply voltage
2 data output 0 to output 3
ground (0 V)
ground (0 V)
supply voltage
ground (0 V)
4 output enable (LOW active)
3 output enable (LOW active)
ground (0 V)
supply voltage
ground (0 V)
ground (0 V)
supply voltage
ground (0 V)
2 output enable (LOW active)
13, 14, 16, 17 3 data output 0 to output 3
19, 20, 22, 23 4 data output 0 to output 3
30, 29, 27, 26 4 data input 0 to input 3
36, 35, 33, 32 3 data input 0 to input 3
41, 40, 38, 37 2 data input 0 to input 3
47, 46, 44, 43 1 data input 0 to input 3
6. Functional description
Table 3.
Control
nOE
L
L
H
[1]
Function table
[1]
Input
nAx
L
H
X
Output
nYx
H
L
Z
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
74ABT16240A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 March 2009
4 of 14
NXP Semiconductors
74ABT16240A
16-bit inverting buffer/line driver; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
j
T
stg
[1]
[2]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
junction temperature
storage temperature
Conditions
[1]
Min
−0.5
−1.2
−0.5
−18
−50
-
-
[2]
Max
+7.0
+7.0
+5.5
-
-
128
−64
150
+150
Unit
V
V
V
mA
mA
mA
mA
°C
°C
output in OFF-state or HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
output in HIGH-state
[1]
-
−65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
8. Recommended operating conditions
Table 5.
Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
Parameter
supply voltage
input voltage
HIGH-level input voltage
LOW-level Input voltage
HIGH-level output current
LOW-level output current
duty cycle
≤
50 %;
f
i
≥
1 kHz
∆t/∆V
T
amb
input transition rise and fall rate
ambient temperature
in free air
Conditions
Min
4.5
0
2.0
-
−32
-
-
-
−40
Typ
-
-
-
-
-
-
-
-
-
Max
5.5
V
CC
-
0.8
-
32
64
10
+85
Unit
V
V
V
V
mA
mA
mA
ns/V
°C
74ABT16240A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 March 2009
5 of 14
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