CAT5269
Dual Digital
Potentiometer (POT)
with 256 Taps
and 2‐wire Interface
Description
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The CAT5269 is two digital POTs integrated with control logic and
18 bytes of NVRAM memory. Each digital POT consists of a series of
resistive elements connected between two externally accessible end
points. The tap points between each resistive element are connected to
the wiper outputs with CMOS switches. A separate 8-bit control
register (WCR) independently controls the wiper tap switches for each
digital POT. Associated with each wiper control register are four 8-bit
non-volatile memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or any of the
non-volatile data registers is via a 2-wire serial bus. On power-up, the
contents of the first data register (DR0) for each of the potentiometers
is automatically loaded into its respective wiper control registers.
The CAT5269 can be used as a potentiometer or as a two terminal,
variable resistor. It is intended for circuit level or system level
adjustments in a wide variety of applications. It is available in the
−40C
to 85C industrial operating temperature range and offered in a
24-lead SOIC and TSSOP package.
Features
TSSOP−24
Y SUFFIX
CASE 948AR
SOIC−24
W SUFFIX
CASE 751BK
PIN CONNECTIONS
NC
A0
NC
NC
NC
NC
V
CC
R
L0
R
H0
R
W0
A2
WP
SOIC−24 (W)
TSSOP−24 (Y)
(Top View)
CAT5269
1
A3
SCL
NC
NC
NC
NC
GND
R
W1
R
H1
R
L1
A1
SDA
Four Linear Taper Digital Potentiometers
256 Resistor Taps per Potentiometer
End to End Resistance 50 kW or 100 kW
Potentiometer Control and Memory Access via 2-wire Interface
(I
2
C like)
Low Wiper Resistance, Typically 100
W
Nonvolatile Memory Storage for up to Four Wiper Settings for Each
Potentiometer
Automatic Recall of Saved Wiper Settings at Power Up
2.5 to 6.0 Volt Operation
Standby Current less than 1
mA
1,000,000 Nonvolatile WRITE Cycles
100 Year Nonvolatile Memory Data Retention
24-lead SOIC and TSSOP Packages
Industrial Temperature Range
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
Semiconductor Components Industries, LLC, 2013
July, 2013
−
Rev. 7
1
Publication Order Number:
CAT5269/D
CAT5269
MARKING DIAGRAMS
(SOIC−24)
(TSSOP−24)
L3B
CAT5269WT
−RRYMXXXX
RLB
CAT5269YT
3YMXXX
L = Assembly Location
3 = Lead Finish
−
Matte-Tin
B = Product Revision (Fixed as “B”)
CAT5269W = Device Code
T = Temperature Range (I = Industrial)
−
= Dash
RR = Resistance
25 = 2.5 KW
10 = 10 KW
50 = 50 KW
00 = 100 KW
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXXX = Last Four Digits of Assembly Lot Number
R = Resistance
1 = 2.5 KW
2 = 10 KW
4 = 50 KW
5 = 100 KW
L = Assembly Location
B = Product Revision (Fixed as “B”)
CAT5269Y = Device Code
T = Temperature Range (I = Industrial)
3 = Lead Finish
−
Matte-Tin
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXX = Last Three Digits of Assembly Lot Number
R
H0
WIPER
CONTROL
REGISTERS
R
H1
SCL
SDA
2−WIRE BUS
INTERFACE
R
W0
WP
A0
A1
A2
A3
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
R
L0
R
L1
R
W1
Figure 1. Functional Diagram
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CAT5269
PIN DESCRIPTIONS
Table 1. PIN DESCRIPTIONS
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
NC
A0
NC
NC
NC
NC
V
CC
R
L0
R
H0
R
W0
A2
WP
SDA
A1
R
L1
R
H1
R
W1
GND
NC
NC
NC
NC
SCL
A3
No Connect
Device Address, LSB
No Connect
No Connect
No Connect
No Connect
Supply Voltage
Low Reference Terminal for
Potentiometer 0
High Reference Terminal for
Potentiometer 0
Wiper Terminal for Potentiometer 0
Device Address
Write Protection
Serial Data Input/Output
Device Address
Low Reference Terminal for
Potentiometer 1
High Reference Terminal for
Potentiometer 1
Wiper Terminal for Potentiometer 1
Ground
No Connect
No Connect
No Connect
No Connect
Bus Serial Clock
Device Address
Function
SCL: Serial Clock
The CAT5269 serial clock input pin is used to clock all data
transfers into or out of the device.
SDA: Serial Data
The CAT5269 bidirectional serial data pin is used to transfer
data into and out of the device. The SDA pin is an open drain
output and can be wire-Ored with the other open drain or
open collector I/Os.
A0, A1, A2, A3: Device Address Inputs
These inputs set the device address when addressing
multiple devices. A total of sixteen devices can be addressed
on a single bus. A match in the slave address must be made
with the address input in order to initiate communication
with the CAT5269.
R
H
, R
L
: Resistor End Points
The two sets of R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer.
R
W
: Wiper
The R
W
pins are equivalent to the wiper terminal of a
mechanical potentiometer.
WP: Write Protect Input
The WP pin when tied low prevents non-volatile writes to
the data register (change of wiper control register is allowed)
and when tied high or left floating normal read/write
operations are allowed. See Write Protection on page 8 for
more details.
DEVICE OPERATION
The CAT5269 is two resistor arrays integrated with a
2-wire serial interface, two 8-bit wiper control registers and
eight 8-bit, non-volatile memory data registers. Each
resistor array contains 255 separate resistive elements
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical
potentiometer (R
H
and R
L
). The tap positions between and
at the ends of the series resistors are connected to the output
wiper terminals (R
W
) by a CMOS transistor switch. Only
one tap point for each potentiometer is connected to its wiper
terminal at a time and is determined by the value of the wiper
control register. Data can be read or written to the wiper
control registers or the non-volatile memory data registers
via the 2-wire bus. Additional instructions allow data to be
transferred between the wiper control registers and each
respective potentiometer’s non-volatile data registers. Also,
the device can be instructed to operate in an “increment/
decrement” mode.
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CAT5269
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to V
SS
(Note 1)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25C)
Lead Soldering Temperature (10 s)
Wiper Current
Ratings
−55
to +125
−65
to +150
−2.0
to +V
CC
+ 2.0
−2.0
to +7.0
1.0
300
6
Units
C
C
V
V
W
C
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. RECOMMENDED OPERATING CONDITIONS
Parameters
V
CC
Industrial Temperature
Ratings
+2.5 to +6.0
−40
to +85
Units
V
C
Table 4. POTENTIOMETER CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
R
POT
R
POT
Parameter
Potentiometer Resistance (100 kW)
Potentiometer Resistance (50 kW)
Potentiometer Resistance Tolerance
R
POT
Matching
Power Rating
I
W
R
W
R
W
V
TERM
Wiper Current
Wiper Resistance
Wiper Resistance
Voltage on any R
H
or R
L
Pin
Resolution
Absolute Linearity (Note 4)
Relative Linearity (Note 5)
TC
RPOT
TC
RATIO
C
H
/C
L
/C
W
fc
Temperature Coefficient of R
POT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
R
w(n)(actual)
−R
(n)(expected)
(Note 7)
R
w(n+1)
−[R
w(n)+LSB
]
(Note 7)
(Note 3)
(Note 3)
(Note 3)
R
POT
= 50 kW (Note 3)
10/10/25
0.4
300
20
I
W
=
3
mA @ V
CC
= 3 V
I
W
=
3
mA @ V
CC
= 5 V
V
SS
= 0 V
V
SS
0.4
1
0.2
200
100
25C, each pot
Test Conditions
Min
Typ
100
50
20
1
50
3
300
150
V
CC
Max
Units
kW
kW
%
%
mW
mA
W
W
V
%
LSB
(Note 6)
LSB
(Note 6)
ppm/C
ppm/C
pF
MHz
1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5 V, which may overshoot to V
CC
+2.0 V for periods of less than 20 ns.
2. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to V
CC
+1 V.
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
5. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.
It is a measure of the error in step size.
6. LSB = R
TOT
/ 255 or (R
H
−
R
L
) / 255, single pot
7. n = 0, 1, 2, ..., 255
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CAT5269
Table 5. D.C. OPERATING CHARACTERISTICS
(V
CC
= +2.5 V to +6.0 V, unless otherwise specified.)
Symbol
I
CC1
I
CC2
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
Parameter
Power Supply Current
Power Supply Current
Non-volatile WRITE
Standby Current (V
CC
= 5 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3 V)
I
OL
= 3 mA
Test Conditions
f
SCL
= 400 kHz, SDA = Open
V
CC
= 6 V, Inputs = GND
f
SCK
= 400 kHz, SDA Open
V
CC
= 6 V, Input = GND
V
IN
= GND or V
CC
, SDA = Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
−1
V
CC
x 0.7
Min
Max
1
5
5
10
10
V
CC
x 0.3
V
CC
+ 1.0
0.4
Units
mA
mA
mA
mA
mA
V
V
V
Table 6. CAPACITANCE
(T
A
= 25C, f = 1.0 MHz, V
CC
= 5 V)
Symbol
C
I/O
(Note 8)
C
IN
(Note 8)
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL, WP)
Conditions
V
I/O
= 0 V
V
IN
= 0 V
Max
8
6
Units
pF
pF
Table 7. A.C. CHARACTERISTICS
2.5 V
−
6.0 V
Symbol
f
SCL
T
I
(Note 8)
t
AA
t
BUF
(Note 8)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
(Note 8)
t
F
(Note 8)
t
SU:STO
t
DH
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the bus must be free before a new transmission can start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0.6
100
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
Parameter
Min
Max
400
200
1
Units
kHz
ns
ms
ms
ms
ms
ms
ms
ns
ns
ms
ns
ms
ns
8. This parameter is tested initially and after a design or process change that affects the parameter.
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