HMXADC9225
Advanced Information
HMXADC9225 – Radiation
Hardened 12-Bit, 20 MSPS
Monolithic A/D Converter
The HMXADC9225 is a radiation hardened monolithic, single
supply, 12-bit, 20 MSPS, analog-to-digital converter with an
on-chip, high performance sample-and-hold amplifier. The
HMXADC9225 uses a multistage differential pipelined
architecture with output error correction logic to provide 12-bit
accuracy at 20 MSPS data rates, and guarantees no missing
codes over the full operating temperature range.
The HMXADC9225 combines a radiation hardened SOI-IV
Silicon On Insulator (SOI) process and very low power
consumption.
A single clock input is used to control all internal
The input of the HMXADC9225 allows for easy interfacing to
space and military imaging, sensor, and communications
systems.
conversion cycles. The digital output data is presented
in straight binary output format.
The sample-and-hold amplifier (SHA) is well suited for
both multiplexed systems that switch full-scale voltage
levels in successive channels and sampling single-
channel inputs at frequencies up to and well beyond
the Nyquist rate.
With a truly differential input structure, the user can
select a variety of input ranges and offsets including
single-ended applications. The dynamic performance
is excellent.
FEATURES
Monolithic 12-Bit, 20 MSPS A/D
Converter
Rad Hard: >1000 krad Total Dose
Low Power Dissipation: 240 mW
Single +5 V Analog Supply
5V or 3.3V Digital and I/O Supply
No Missing Codes Guaranteed
Differential Nonlinearity Error: 0.4
LSB
Complete On-Chip S/H Amplifier
Signal-to-Noise and Distortion
Ratio: 69.6 dB
Spurious-Free Dynamic Range:
–81 dB
Straight Binary Output Data
28-Lead Ceramic Flat Pack
Mixed Signal Rad Hard Process
The HMXADC9225 is fabricated on
space qualified SOI CMOS process.
High-speed precision analog circuits
are now combined with high-density
logic circuits that can reliably
withstand the harshest environments.
Space Qualified Package
The HMXADC9225 is packaged in a
28 lead ceramic flat pack.
Low Power
The HMXADC9225 at 240 mW
consumes a fraction of the power of
presently available in existing
monolithic solutions.
Output Enable (OE)
The OE input allows user to put the
digital outputs into a high impedance
tri-state mode.
Dual Power Supply Capability
The HMXADC9225 uses a single +5
V power supply simplifying system
power supply design. It also features
a separate digital driven supply line to
accommodate 3 V and 5 V logic
families.
On-Board Sample-and-Hold (SHA)
The versatile SHA input can be
configured for either single-ended or
differential inputs.
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HMXADC9225
Advanced Information
BLOCK DIAGRAM
REFP, REFN
VINP
S/H
VINN
MDAC1
X16
MDAC2
X4
MDAC3
X4
Correct
Logic
Data
Output
Drivers
Output
Tri-State
Control
D0 – D11
DRVDD
DRVSS
A/D
A/D
A/D
A/D
5
Clock
Clock
Gen
CML
Gen
Master Bias
IREF
3
3
4
Output
Enable
CML
Diff
Buffer
REFP
REFN
AVDD
AVSS
REFCOM
RBIAS
VREF
5kΩ
External
Reference
Input
Cext
PIN DESCRIPTION
Pin
1
2
3-12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin Name
CLK
BIT 12
BIT 11 – 2
BIT 1
OE
AVDD
AVSS
RBIAS
VREF INPUT
REFCOMM
CAPB
CAPT
CML
VINA
VINB
AVSS
AVDD
DRVSS
DRDVDD
Description
Clock Input
Least Significant Data Bit (LSB)
Data Output Bit
Most Significant Bit (MSB)
Output Enable (high active)
+5V Analog Supply
Analog Ground
Reference Current Bias Resistor
Reference Voltage Input
Reference Common
Noise Reduction Pin
Noise Reduction Pin
Common Mode Level
Analog Input (+)
Analog Input (-)
Analog Ground
+5V Analog Supply
Digital Output Driver Ground
+5V or 3.3V Digital Output Driver Supply
1 CLK
2
3
4
5
6
7
8
9
BIT 12 (LSB)
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT5
DRVDD 28
DRVSS
AVDD
27
26
AVSS 25
VIN B 24
VIN A
23
CML 22
CAPT 21
CAPB
20
10 BIT 4
11 BIT 3
12 BIT 2
13 BIT 1 (MSB)
14 OE
REFCOM 19
VREF IN 18
RBIAS 17
AVSS 16
AVDD 15
SIGNAL DEFINITION
DRVDD
The DRVDD power supply can be either 5.0V or
3.3V. The voltage used will also define the voltage
level of all of the following digital I/O signals including
Clock, Output Enable, all data output signals.
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OUTPUT ENABLE (OE)
This signal will control the digital output signals. A
high logic level will enable the outputs and a low logic
level will put the outputs into a high impedance state.
HMXADC9225
Advanced Information
TIMING DIAGRAM
S1
Analog
Input
S2
t
C
t
CH
t
CL
t
CD
Data 1
S3
S4
Clock
Data
Out
RADIATION PERFORMANCE
Total Ionizing Radiation Dose
The HMXADC9225 will meet all stated functional
and electrical specifications over the entire
operating temperature range after the specified
total ionizing radiation dose. All electrical and
timing performance parameters will remain within
specifications after rebound at VDD = 5.0 V and
T =125°C extrapolated to ten years of operation.
Total dose hardness is assured by wafer level
testing of process monitor transistors using 10
KeV X-ray and Co60 radiation sources.
Transistor gate threshold shift correlations have
been made between 10 KeV X-rays applied at a
dose rate of 1x10
5
rad(SiO
2
)/min at T = 25°C and
gamma rays (Cobalt 60 source) to ensure that
wafer level X-ray testing is consistent with
standard military radiation test environments.
Transient Pulse Ionizing Radiation
The HMXADC9225 is capable of writing, reading,
and retaining stored data during and after
exposure to a transient ionizing radiation pulse,
up to the specified transient dose rate upset
specification, when applied under recommended
operating conditions. To ensure validity of all
specified performance parameters before, during,
and after radiation (timing degradation during
transient pulse radiation is
±10%),
it is suggested
that stiffening capacitance be placed near the
package VDD and VSS. If there are no operate
through or valid stored data requirements, typical
circuit board mounted de-coupling capacitors are
recommended.
The HMXADC9225 will meet any functional or
electrical specification after exposure to a
radiation pulse up to the transient dose rate
survivability specification, when applied under
recommended operating conditions. Note that the
current conducted during the pulse by the ADC
inputs, outputs, and power supply may
significantly exceed the normal operating levels.
The application design must accommodate these
effects.
Neutron Radiation
The HMXADC9225 will meet any functional or
timing specification after exposure to the
specified neutron fluence under recommended
operating or storage conditions. This assumes
equivalent neutron energy of 1 MeV.
Soft Error Rate
The HMXADC9225 is capable of meeting the
specified Soft Error Rate (SER), under
recommended operating conditions. This
hardness level is defined by the Adams 90%
worst case cosmic ray environment for
geosynchronous orbits.
Latchup
The HMXADC9225 will not latch up due to any of
the above radiation exposure conditions when
applied under recommended operating
conditions. Fabrication with the SIMOX substrate
material provides oxide isolation between
adjacent PMOS and NMOS transistors and
eliminates any potential SCR latchup structures.
Sufficient transistor body tie connections to the p-
and n-channel substrates are made to ensure no
source/drain snapback occurs.
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HMXADC9225
Advanced Information
RADIATION SPECIFICATIONS
(T
MIN
to T
MAX
Parameters
Total Dose Hardness
Dose Rate Upset Hardness
Dose Rate Survivability
Soft Error Rate
Nuetron Fluence Hardness
with AVDD = +5V, DRVDD = +5V, C
L
= 20 pF)
Min
>1 x 10
TBD
TBD
TBD
6
Max
Units
Rad (SiO
2
)
Rad(Si)/sec
Rad(Si)/sec
Errors/bit/day
/cm
2
TBD
Absolute Maximum Ratings
Parameters
AVDD
DRVDD
AVSS
REFCOMM
CLK
Digital Outputs
VINA, VINB
VREF
CAPB, CAPT
Junction Temperature
Operating Temperature
(AVDD = +5V, DRVDD = +5V, unless otherwise noted)
Min
-0.3
-0.3
Max
5.5
5.5
5.5
5.5
5.5
5.5
5.5
+175
+125
Units
V
V
V
V
V
V
V
V
V
o
C
o
C
-55
Recommended Operating Conditions
Parameter
AVDD (Supply Voltage)
DRVDD (Supply Voltage, 5.0V)
DRVDD (Supply Voltage, 3.3V)
TA (Ambient Temperature)
Vpin (Voltage on any pin referenced to VSS)
Min
4.5
4.5
3.0
-55
-0.3
Typical
5.0
5.0
3.3
25
Max
5.5
5.5
3.6
125
VDD+0.3
Units
V
V
V
°C
V
ESD (Electrostatic Discharge) Sensitive
The HMXADC9225 is sensitive to ESD above levels
of 2000 volts. Proper ESD precautions should be
taken to avoid degradation or damage to the device.
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HMXADC9225
Advanced Information
DC SPECIFICATIONS
(AVDD = +5V, DRVDD = +5V, f
SAMPLE
= 20 MSPS, VREF 2.0V, VINB = 2.5V dc, T
MIN
to T
MAX
unless otherwise noted)
Parameter
Min
Typical Max
Units
RESOLUTION
MAX CONVERSION RATE
INPUT REFERRED NOISE
VREF = 2.0V
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
No Missing Codes
Zero Error (@ +25°C)
Gain Error (@ +25°C)
1
Gain Error (@ +25°C)
2
Temperature Drift
Zero Error (@ +25°C)
Gain Error (@ +25°C)
1
Gain Error (@ +25°C)
2
ANALOG INPUT
Input Span
Input Capacitance
EXTERNAL VOLTAGE REFERENCE
Input Voltage
Input Voltage Tolerance
Current
R-Bias Resistor
Cext
3
12
20
0.17
±1.2
±0.4
12
±0.3
±0.5
±0.4
TBD
TBD
TBD
Bits
MHz
LSB rms
LSB
LSB
Bits Guaranteed
% FSR
% FSR
% FSR
ppm/
o
C
ppm/
o
C
ppm/
o
C
4
TBD
2.0
±10
250
5k
1 and 10
V p-p
pF
V
mV
µA
Ohms (+/- 5%)
µF (in parallel)
±35
500
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD (5.0V)
DRVDD (3.3V)
Supply Currents
IAVDD
IDRVDD
POWER CONSUMPTION
External Reference
NOTES
1
Includes internal voltage reference error.
2
Excludes internal voltage reference error.
3
Cext should consist of a 1uF and 10 uF in parallel.
Specifications subject to change without notice.
4.75
4.75
3.0
5.0
5.0
3.3
67
2.0
335
5.25
5.25
3.6
V (±5%
AVDD Operating)
V (±5%
DRVDD Operating
)
V
mA
mA
mW
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