IDT74FCT162823AT/CT
FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS 18-BIT
REGISTER
IDT74FCT162823AT/CT
FEATURES:
•
•
•
•
•
•
•
•
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical t
SK(o)
(Output Skew) < 250ps
Low input and output leakage
≤
1µA (max.)
V
CC
= 5V ±10%
Balanced Output Drivers of ±24mA
Reduced system switching noise
Typical V
OLP
(Output Ground Bounce) < 0.6V at V
CC
= 5V,
T
A
= 25°C
• Available in SSOP and TSSOP packages
DESCRIPTION:
The FCT162823T 18-bit bus interface register is built using advanced, dual
metal CMOS technology. These high-speed, low-power registers with clock
enable (xCLKEN) and clear (xCLR) controls are ideal for parity bus interfacing
in high-performance synchronous systems. The control inputs are organized
to operate the device as two 9-bit registers or one 18-bit register. Flow-through
organization of signal pins simplifies layout. All inputs are designed with
hysteresis for improved noise margin.
The FCT162823T has balanced output drive with current limiting resistors.
This offers low ground bounce, minimal undershoot, and controlled output fall
times – reducing the need for external series terminating resistors. The
FCT162823T is a plug-in replacement for the FCT16823T and ABT16823 for
on-board interface applications.
FUNCTIONAL BLOCK DIAGRAM
2
1
OE
1
CLR
1
CLK
55
1
CLKEN
2
CLKEN
1
56
2
CLK
2
OE
2
CLR
27
28
29
30
R
C
D
54
1
D
1
2
D
1
3
1
Q
1
42
R
C
D
15
2
Q
1
TO EIGHT OTHER CHANNELS
TO EIGHT OTHER CHANNELS
INDUSTRIAL TEMPERATURE RANGE
1
© 2006 Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
JUNE 2006
DSC-5437/6
IDT74FCT162823AT/CT
FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
CLR
1
OE
1
Q
1
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to 7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
CLK
1
CLKEN
1
D
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
TERM(2)
Terminal Voltage with Respect to GND
V
TERM(3)
T
STG
I
OUT
GND
1
Q
2
1
Q
3
GND
1
D
2
1
D
3
V
CC
1
Q
4
1
Q
5
1
Q
6
V
CC
1
D
4
1
D
5
1
D
6
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Outputs and I/O terminals for FCT162XXX.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
Max.
6
8
Unit
pF
pF
GND
1
Q
7
1
Q
8
1
Q
9
2
Q
1
2
Q
2
2
Q
3
GND
1
D
7
1
D
8
1
D
9
2
D
1
2
D
2
2
D
3
NOTE:
1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names
xDx
xCLK
xCLKEN
xCLR
xOE
xOx
Data Inputs
Clock Inputs
Clock Enable Inputs (Active LOW)
Asynchronous clear Inputs (Active LOW)
Output Enable Inputs (ActiveLOW)
3-State Outputs
Description
GND
2
Q
4
2
Q
5
2
Q
6
GND
2
D
4
2
D
5
2
D
6
V
CC
2
Q
7
2
Q
8
V
CC
2
D
7
2
D
8
GND
2
Q
9
2
OE
2
CLR
GND
2
D
9
2
CLKEN
2
CLK
FUNCTION TABLE
(1)
xOE
H
L
L
H
H
L
L
xCLR
X
L
H
H
H
H
H
Inputs
xCLKEN
X
X
H
L
L
L
L
xCLK
X
X
X
↑
↑
↑
↑
xDx
X
X
X
L
H
L
H
Outputs
xQx
Z
L
Q
(2)
Z
Z
L
H
Function
High Z
Clear
Hold
Load
SSOP/ TSSOP
TOP VIEW
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
2. Output level before indicated steady-state input conditions were established.
2
IDT74FCT162823AT/CT
FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
OS
V
H
I
CCL
I
CCH
I
CCZ
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current (Input pins)
(4)
Input HIGH Current (I/O pins)
(4)
Input LOW Current (Input pins)
(4)
Input LOW Current (I/O pins)
(4)
High Impedance Output Current
(3-State Output pins)
(4)
Clamp Diode Voltage
Short Circuit Current
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max
V
IN
= GND or V
CC
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
—
V
CC
= Max.
V
O
= 2.7V
V
O
= 0.5V
V
I
= GND
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
Min.
2
—
—
—
—
—
—
—
—
–80
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
–0.7
–140
100
5
Max.
—
0.8
±1
±1
±1
±1
±1
±1
–1.2
–250
—
500
V
mA
mV
µA
µA
Unit
V
V
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
I
ODL
I
ODH
V
OH
V
OL
Parameter
Output LOW Current
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
Test Conditions
(1)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
O
= 1.5V
(3)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
O
= 1.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= Min.
V
IN
= V
IH
or V
IL
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This test limit for this parameter is ±5µA at T
A
= –55°C.
Min.
60
–60
2.4
—
Typ.
(2)
115
–115
3.3
0.3
Max.
200
–200
—
0.55
Unit
mA
mA
V
V
I
OH
= –24mA
I
OL
= 24mA
3
IDT74FCT162823AT/CT
FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
ΔI
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
xOE = xCLKEN = GND
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
xOE = xCLKEN = GND
at fi = 5MHz
50% Duty Cycle
One Bit Toggling
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
xOE = xCLKEN = GND
at fi = 2.5MHz
50% Duty Cycle
Eighteen Bits Toggling
V
IN
= V
CC
V
IN
= GND
Min.
—
—
Typ.
(2)
0.5
75
Max.
1.5
120
Unit
mA
µA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
—
0.8
1.7
mA
V
IN
= 3.4V
V
IN
= GND
—
1.3
3.2
V
IN
= V
CC
V
IN
= GND
—
4.2
7.1
(5)
V
IN
= 3.4V
V
IN
= GND
—
9.2
22.1
(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
ΔI
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + fiNi)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
ΔI
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
4
IDT74FCT162823AT/CT
FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
t
PLH
Propagation Delay
t
PHL
xCLKx to xOx
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(4)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(4)
R
L
= 500Ω
C
L
= 50pF
(4)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
FCT162823AT
Min.
(2)
Max.
1.5
10
1.5
1.5
1.5
1.5
1.5
1.5
3
1.5
3
0
6
6
6
—
20
14
12
23
7
8
—
—
—
—
—
—
—
0.5
FCT162823CT
Min.
(2)
Max.
1.5
4.7
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0
2.5
0
3
3
3
—
8
4.7
4.4
9
3.6
3.6
—
—
—
—
—
—
—
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
t
PHL
t
PZH
t
PZL
Propagation Delay
xCLR to xQx
Output Enable Time
xOE to xOx
t
PHZ
t
PLZ
Output Disable Time
xOE to xOx
t
SU
t
H
t
SU
t
H
t
W
t
W
t
REM
t
SK(o)
Set-up Time HIGH or LOW xDx to xCLK
Hold Time HIGH or LOW, xDx to xCLK
Set-up Time HIGH or LOW, xCLKEN to xCLK
Hold Time HIGH or LOW, xCLKEN to xCLK
xCLK Pulse Width HIGH or LOW
xCLR Pulse Width LOW
Recovery Time, xCLR to xCLK
Output Skew
(3)
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
4. This condition is guaranteed but not tested.
5
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