74ALVC16722 Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs
December 2001
Revised December 2001
74ALVC16722
Low Voltage 22-Bit Register
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16722 low voltage 22-bit register contains
twenty-two non-inverting D-type flip-flops with 3-STATE
outputs and is intended for bus oriented applications. The
design has been optimized for use with JEDEC compliant
200 pin DIMM modules.
The 74ALVC16722 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O capability up to 3.6V.
The 74ALVC16722 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
1.65V to 3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
t
PD
(CLK to O
n
)
4.1ns max for 3.0V to 3.6V V
CC
5.1ns max for 2.3V to 2.7V V
CC
9.2ns max for 1.65V to 1.95V V
CC
s
Power-off high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
Meets JEDEC registered module specifications
s
Latchup conforms to JEDEC JED78
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current sourcing capability of the
driver.
Ordering Code:
Order Number
74ALVC16722MTD
Package Number
MTD64
Package Description
64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2001 Fairchild Semiconductor Corporation
DS500715
www.fairchildsemi.com
74ALVC16722
Connection Diagram
Pin Descriptions
Pin Names
OE
CE
CLK
D
0
- D
21
O
0
- O
21
Description
Output Enable Input (Active LOW)
Clock Enable Input (Active Low)
Clock Input
Data Inputs
3-STATE Outputs
Truth Table
CLK
X
X
CE
X
H
L
L
L
OE
H
L
L
L
L
D
n
X
X
L
H
X
O
n
Z
O
n
L
H
O
n
↑
↑
L or H
H
=
Logic HIGH
L
=
Logic LOW
X
=
Don’t Care, but not floating
Z
=
High Impedance
O
n
=
Previous O
n
before LOW-to-HIGH Clock Transition
↑ =
LOW-to-HIGH Clock Transition
Functional Description
The ALVC16722 contains twenty-two D-type flip-flops with
3-STATE standard outputs. The twenty-two flip-flops will
store the state of their individual D-type inputs that meet
the setup and hold time requirements on the LOW-HIGH
Clock (CLK) transition, when the Clock-Enable (CE) is
LOW. The 3-STATE standard outputs are controlled by the
Output-Enable (OE). When OE is HIGH, the standard out-
puts are in high impedance mode but this does not inter-
fere with entering new data into the flip-flops.
Logic Diagram
www.fairchildsemi.com
2
74ALVC16722
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
Output Voltage (V
O
) (Note 3)
DC Input Diode Current (I
IK
)
V
I
<
0V
DC Output Diode Current (I
OK
)
V
O
<
0V
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
Storage Temperature Range (T
STG
)
−
0.5V to
+
4.6V
−
0.5V to 4.6V
−
0.5V to V
CC
+
0.5V
−
50 mA
−
50 mA
±
50 mA
±
100 mA
−
65
°
C to
+
150
°
C
Recommended Operating
Conditions
(Note 4)
Power Supply
Operating
Input Voltage (V
I
)
Output Voltage (V
O
)
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (
∆
t/
∆
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Note 2:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 3:
I
O
Absolute Maximum Rating must be observed.
Note 4:
Floating or unused inputs must be held HIGH or LOW.
1.65V to 3.6V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level Input Voltage
Conditions
V
CC
(V)
1.65 -1.95
2.3 - 2.7
2.7 - 3.6
V
IL
LOW Level Input Voltage
1.65 -1.95
2.3 - 2.7
2.7 - 3.6
V
OH
HIGH Level Output Voltage
I
OH
= −100 µA
I
OH
= −4
mA
I
OH
= −6
mA
I
OH
= −12
mA
1.65 - 3.6
1.65
2.3
2.3
2.7
3.0
I
OH
= −24
mA
V
OL
LOW Level Output Voltage
I
OL
=
100
µA
I
OL
=
4 mA
I
OL
=
6 mA
I
OL
=
12mA
I
OL
=
24 mA
I
I
I
OZ
I
CC
∆I
CC
Input Leakage Current
3-STATE Output Leakage
Quiescent Supply Current
Increase in I
CC
per Input
0
≤
V
I
≤
3.6V
0
≤
V
O
≤
3.6V
V
I
=
V
CC
or GND, I
O
=
0
V
IH
=
V
CC
−
0.6V
3.0
1.65 - 3.6
1.65
2.3
2.3
2.7
3
3.6
3.6
3.6
3 -3.6
V
CC
- 0.2
1.2
2
1.7
2.2
2.4
2
0.2
0.45
0.4
0.7
0.4
0.55
±5.0
±10
40
750
µA
µA
µA
µA
V
V
Min
0.65 x V
CC
1.7
2.0
0.35 x V
CC
0.7
0.8
V
V
Max
Units
3
www.fairchildsemi.com
74ALVC16722
AC Electrical Characteristics
T
A
= −40°C
to
+85°C,
R
L
=
500Ω
Symbol
Parameter
C
L
=
50 pF
V
CC
=
3.3V
±
0.3V
Min
f
MAX
t
PHL
, t
PLH
t
PZL
, t
PZH
t
PLZ
, t
PHZ
t
W
t
S
t
H
Maximum Clock Frequency
Propagation Delay
CLK to Bus
Output Enable Time
Output Disable Time
Pulse Width
Setup Time
Hold Time
250
1.3
1.1
1.1
1.5
2.0
0.0
4.1
4.0
3.7
Max
V
CC
=
2.7V
Min
200
2.0
1.3
1.3
1.5
2.0
0.0
5.1
5.0
4.7
Max
C
L
=
30 pF
V
CC
=
2.5V
±
0.2V
Min
200
1.5
0.8
0.8
1.5
2.0
0.0
4.6
4.5
4.2
Max
V
CC
=
1.8V
±
0.15V
Min
100
2.0
1.5
1.5
4.0
3.0
0.5
9.2
9.0
7.6
Max
ns
ns
ns
ns
ns
ns
ns
Units
Capacitance
Symbol
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Parameter
V
I
=
0V or V
CC
V
I
=
0V or V
CC
Outputs Enabled f
=
10 MHz, C
L
=
50 pF
Conditions
T
A
= +25°C
V
CC
3.3
3.3
3.3
2.5
Typical
3.5
5.5
13
13
Units
pF
pF
pF
I
OUT
- V
OUT
Characteristics
I
OH
versus V
OH
I
OL
versus V
OL
FIGURE 1. Characteristics for
Output - Pull Up Driver
FIGURE 2. Characteristics for
Output - Pull Down Driver
www.fairchildsemi.com
4
74ALVC16722
AC Loading and Waveforms
TABLE 1. Values for Figure 1
TEST
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
, t
PHZ
SWITCH
Open
V
L
GND
FIGURE 3. AC Test Circuit
TABLE 2. Variable Matrix
(Input Characteristics: f
=
1MHz; t
r
=
t
f
=
2ns; Z
0
=
50
Ω
Symbol
V
mi
V
mo
V
X
V
Y
V
L
V
CC
3.3V
±
0.3V
1.5V
1.5V
V
OL
+
0.3V
V
OH
−
0.3V
6V
2.7V
1.5V
1.5V
V
OL
+
0.3V
V
OH
−
0.3V
6V
2.5V
±
0.2V
V
CC
/2
V
CC
/2
V
OL
+
0.15V
V
OH
−
0.15V
V
CC
*2
1.8V
±
0.15V
V
CC
/2
V
CC
/2
V
OL
+
0.15V
V
OH
−
0.15V
V
CC
*2
FIGURE 4. Waveform for Inverting and
Non-inverting Functions
t
r
=
t
f
≤
2.0ns, 10% to 90%
FIGURE 5. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
t
r
=
t
f
≤
2.0ns, 10% to 90%
FIGURE 6. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
t
r
=
t
f
≤
2.0ns, 10% to 90%
5
www.fairchildsemi.com
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
