Integrated
Circuit
Systems, Inc.
ICS91719
Low EMI, Spread Modulating, Clock Generator
Features:
•
ICS91719 is a Spread Spectrum Clock targeted for
Mobile PC and LCD panel applications. Generates an
EMI optimized clock signal (EMI peak reduction of 7-
14 dB on 3rd-19th harmonics) through use of Spread
Spectrum techniques.
•
ICS91719 focuses on the lower input frequency
range of 14.318 to 80.00 MHz with a spread
modulation of 20kHz to 40kHz.
Specifications:
•
Supply Voltages: VDD = 3.3V ±0.3V
•
Frequency range: 14.318 MHz
≤
Fin
≥
80 MHz
•
Cyc to Cyc jitter: <150ps
•
Output duty cycle 40/60% (worst case)
•
Guarantees +85°C operational condition.
•
16-pin TSSOP package 4.4mm body (173mils), 0.65
mm pitch
•
14.318 MHz crystal input or reference clock input
•
27MHz, 48MHz and 66MHz reference clock input
Pin Configuration
GND
X1_CLKIN
X2
GNDA
VDDA
VDD
GND
* * CLKOUT/FS_IN0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDREF
VDDREF_SEL_2.5V/3.3V# ^
REF_OUT/VDDREF_SEL_1
.8V
**REF_Sto p
^P D#
SCLK
SDA TA
^SP REA D_ENA B LE/FS_IN1
16-pin TSSOP
Notes:
** Internal pull-down
^ Internal pull-up
Input Select Functionality
FS_IN1
0
0
1
1
FS_IN0
0
1
0
1
MHZ
14.318 in 27.00 out
14.318 in/out
27.00 in/out
48.00 in/out
66.66 in/out
Default Spread %
-0.8% downspread
-0.8% downspread
-0.8% downspread
-0.8% downspread
Block Diagram
REFOUT
CLKIN
PLL1
Spread
Spectrum
Spectrum
CLKOUT
CLKOUT
REF Voltage Select Functionality
Pin14
0
0
1
1
Pin15
0
1
0
1
REF Voltage
N/A
1.8V
2.5V
3.3V
SPREAD#
PD#
REF_STOP
SDAT
SD A
SCLK
FS_IN0:1
Control
Logic
Config.
Reg.
0506C—07/28/03
ICS91719
Pin Descriptions
PIN # PIN NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
X1 _CLKIN
X2
GNDA
VDDA
VDD
GND
CLKOUT
FS_IN0
^SPREAD_ENABLE
FS_IN1
SDATA
SCLK
^PD#
**REF_Stop
REF_OUT/VDDREF_SEL_1.8V * *
VDDREF_SEL_2.5V/3.3V# ^
VDDREF
PIN TYPE DESCRIPTION
PWR
IN
OUT
PWR
PWR
PWR
PWR
OUT
IN
IN
IN
IN
IN
IN
IN/OUT
PWR
PWR
Ground pin for 3V outputs
Crystal input or CLOCKIN input
Crystal output
Analog ground
Analog power supply for 3V
Power supply for 3V
Ground pin for 3V outputs
Modulated clock output
Latched input for input frequency select
Spread enable pin
Latched input for input frequency select
Data pin for I2C circuitry 5V tolerant
Clock pin for I2C circuitry 5V tolerant
Power down
Stop control for REF_CLOCK output STOP:1, RUNNING:0
REF_CLOCK output
REF_CLOCK power supply voltage select
Power supply for REF_CLOCK
^internal pull-up
**internal pull-down
0506C—07/28/03
2
ICS91719
Table 1: Frequency Configuration Table
(See I2C Byte 0)
FS4 FS3 FS2 FS1 FS0 Sprd Type Sprd %
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
DOWN
1
0
1 SPREAD
(-)
0
1
Center
0
Spread (+/-)
1
0
1
0
DOWN
1
0
SPREAD
1
(-)
0
1
0
1
0
1
CENTER
0
SPREAD
1
(+/-)
0
1
0
DOWN
1
0
1 SPREAD
(-)
0
1
Center
0
1
Spread (+/-)
0.60
0.80
1.00
1.25
1.50
2.00
0.50
1.00
0.60
0.80
1.00
1.25
1.50
1.75
2.00
2.50
3.00
0.30
0.40
0.50
0.70
1.00
1.20
1.50
0.60
0.80
1.00
1.25
1.50
2.00
0.50
1.00
14in/27out
14in/14ou
t
27in/27ou
t
48in/48ou
t
66in/66ou
t
0506C—07/28/03
3
ICS91719
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
•
•
•
•
•
•
•
•
•
•
Controller
Controller
ICS clock
Controller
ICS clock
Controller
ICS clock
Controller
(host) sends a start bit.
(host) sends the write address D2
(H)
will
acknowledge
(host) sends a dummy command code
will
acknowledge
(host) sends a dummy byte count
will
acknowledge
(host) starts sending first byte (Byte 0)
through byte 6
ICS clock will
acknowledge
each byte
one at a
time
.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2
(H)
Dummy Command Code
ICS (Slave/Receiver)
How to Read:
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the
byte count
Controller (host) acknowledges
ICS clock sends first byte
(Byte 0) through byte 7
Controller (host) will need to acknowledge each
byte
Controller (host) will send a stop bit
How to Read:
Controller (Host)
Start Bit
Address
D3
(H)
ICS (Slave/Receiver)
ACK
ACK
Dummy Byte Count
ACK
ACK
Byte Count
Byte 0
ACK
Byte 0
ACK
Byte 1
ACK
Byte 1
ACK
Byte 2
ACK
Byte 2
ACK
Byte 3
ACK
Byte 3
ACK
Byte 4
ACK
Byte 4
ACK
Byte 5
ACK
Byte 5
ACK
Byte 6
ACK
Byte 6
ACK
Byte 7
ACK
Byte 7
Stop Bit
ACK
Stop Bit
Notes:
1.
2.
3.
4.
5.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
6.
0506C—07/28/03
4
ICS91719
Byte 0:
TYPE
BYTE
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Affected Pin
Pin #
Name
-
-
FS0
FS1
FS2
FS3
FS4
PD# Tri_Sate
Spread Enable
Control Function
Spread/FS0
Spread/FS1
Spread/FS2
Spread/FS3
FS4
PD# Tri_Sate
Spread Enable
Spread Spectrum Control
FS 3:4 Hard/Software
Select
Bit Control
0
1
PWD
RW
RW
RW
R
R/R
W
RW
RW
1
0
0
0
0
1
1
Hi-Z
OFF
LOW
ON
Bit 0
HW/SW Control
RW
HW
SW
0
Byte 1:
TYPE
BYTE
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Affected Pin
Pin #
Name
-
Reserved
SLEW
FS-IN_1 Readback
FS-IN_0 Readback
SLEW
CLK_OUT_Enable
REF_OUT_Enable
Reserved
Control Function
Reserved
Slew Rate REF-OUT
FS-IN_1 Readback
FS-IN_0 Readback
Slew Rate CLK-OUT
CLK_OUT_Enable
REF_OUT_Enable
Reserved
Bit Control
0
1
PWD
R
-
-
RW Nominal Fast
Not
RW Freerun Freerun
RW Nominal Fast
RW Nominal Fast
RW Disable Enable
RW Disable Enable
R
-
-
1
1
1
1
1
1
1
1
Byte 2:
TYPE
BYTE
2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Affected Pin
Pin #
Name
x
x
x
x
x
x
x
x
-
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Bit Control
0
1
-
Disable
Disable
Disable
Disable
Disable
Disable
Disable
-
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
-
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
0506C—07/28/03
5
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