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9112AM-17: 产品描述PLL Based Clock Driver, 9112 Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, MS-012, SOIC-16; 产品类别逻辑逻辑; 文件大小163KB，共12页; 制造商IDT (Integrated Device Technology)

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9112AM-17概述

PLL Based Clock Driver, 9112 Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, MS-012, SOIC-16

9112AM-17规格参数

参数名称	属性值
是否无铅	含铅
是否Rohs认证	不符合
厂商名称	IDT (Integrated Device Technology)
零件包装代码	SOIC
包装说明	SOP, SOP16,.25
针数	16
Reach Compliance Code	not_compliant

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Integrated

Circuit

Systems, Inc.

ICS9112-17

Low Skew Output Buffer

General Description

The

ICS9112-17

is a high performance, low skew, low jitter

zero delay buffer. It uses a phase lock loop (PLL)

technology to align, in both phase and frequency, the REF

input with the CLKOUT signal. It is designed to distribute

high speed clocks in PC systems operating at speeds

from 25 to 133 MHz.

ICS9112-17

is a zero delay buffer that provides

synchronization between the input and output. The

synchronization is established via CLKOUT feed back to

the input of the PLL. Since the skew between the input and

output is less than +/- 350 pS, the part acts as a zero delay

buffer.

The

ICS9112-17

has two banks of four outputs controlled

by two address lines. Depending on the selected address

line, bank B or both banks can be put in a tri-state mode.

In this mode, the PLL is still running and only the output

buffers are put in a high impedance mode. The test mode

shuts off the PLL and connects the input directly to the

output buffers (see table below for functionality).

The

ICS9112-17

comes in a sixteen pin 150 mil SOIC or

16 pin SSOP package. In the absence of REF input, will

be in the power down mode. In this mode, the PLL is turned

off and the output buffers are pulled low. Power down mode

provides the lowest power consumption for a standby

condition.

Features

•

Zero input - output delay

Frequency range 25 - 133 MHz (3.3V)

High loop filter bandwidth ideal for Spread Spectrum

applications.

Less than 200 ps cycle to cycle Jitter

Skew controlled outputs

Skew less than 250 ps between outputs

Available in 16 pin, 150 mil SSOP & SOIC package

Pin Configuration

Block Diagram

16 pin SSOP & SOIC

Functionality

FS2 FS1

CLKA

(1, 4)

Driven

CLKB

(1, 4)

Tristate

CLKOUT

Driven

PLL

Bypass

Mode

Driven

Output

Source

PLL

REF

PLL

Shutdown

Tristate Tristate

PLL

Bypass Bypass

Mode

Driven

0051J—02/05/04

9112AM-17相似产品对比

	9112AM-17	9112AF-17T	ICS9112AF-17-T	ICS9112AF-17T	9112AM-17T	ICS9112AM-17T	ICS9112AF-17	ICS9112AF-17LF-T	ICS9112AM-17	9112AF-17
描述	PLL Based Clock Driver, 9112 Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, MS-012, SOIC-16	PLL Based Clock Driver, 9112 Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, MO-137, SSOP-16	9112 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, 0.150 INCH, MO-137, SSOP-16	PLL Based Clock Driver, 9112 Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, MO-137, SSOP-16	PLL Based Clock Driver, 9112 Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, MS-012, SOIC-16	PLL Based Clock Driver, 9112 Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, MS-012, SOIC-16	PLL Based Clock Driver, 9112 Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, MO-137, SSOP-16	9112 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, 0.150 INCH, MO-137, GREEN, SSOP-16	PLL Based Clock Driver, 9112 Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, MS-012, SOIC-16	PLL Based Clock Driver, 9112 Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, MO-137, SSOP-16
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合	不符合	符合	不符合	不符合
厂商名称	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
零件包装代码	SOIC	SSOP	SSOP	SSOP	SOIC	SOIC	SSOP	SSOP	SOIC	SSOP
包装说明	SOP, SOP16,.25	SSOP, SSOP16,.25	SSOP,	SSOP, SSOP16,.25	SOP, SOP16,.25	SOP, SOP16,.25	SSOP, SSOP16,.25	SSOP,	SOP, SOP16,.25	SSOP, SSOP16,.25
针数	16	16	16	16	16	16	16	16	16	16
Reach Compliance Code	not_compliant	not_compliant	compliant	not_compliant	not_compliant	not_compliant	not_compliant	compliant	not_compliant	not_compliant
其他特性	-	ALSO OPERATES WITH 5V SUPPLY	ALSO OPERATES WITH 5V SUPPLY	ALSO OPERATES WITH 5V SUPPLY	ALSO OPERATES WITH 5V SUPPLY	ALSO OPERATES WITH 5V SUPPLY	ALSO OPERATES WITH 5V SUPPLY	ALSO OPERATES WITH 5V SUPPLY	ALSO OPERATES WITH 5V SUPPLY	ALSO OPERATES WITH 5V SUPPLY
系列	-	9112	9112	9112	9112	9112	9112	9112	9112	9112
输入调节	-	STANDARD	STANDARD	STANDARD	STANDARD	STANDARD	STANDARD	STANDARD	STANDARD	STANDARD
JESD-30 代码	-	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16
JESD-609代码	-	e0	e0	e0	e0	e0	e0	e3	e0	e0
长度	-	4.9 mm	4.9 mm	4.9 mm	9.9 mm	9.9 mm	4.9 mm	4.9 mm	9.9 mm	4.9 mm
逻辑集成电路类型	-	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
最大I（ol）	-	0.008 A	-	0.008 A	0.008 A	0.008 A	0.008 A	-	0.008 A	0.008 A
湿度敏感等级	-	1	-	1	1	1	1	-	1	1
功能数量	-	1	1	1	1	1	1	1	1	1
端子数量	-	16	16	16	16	16	16	16	16	16
实输出次数	-	8	8	8	8	8	8	8	8	8
最高工作温度	-	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
输出特性	-	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	-	SSOP	SSOP	SSOP	SOP	SOP	SSOP	SSOP	SOP	SSOP
封装等效代码	-	SSOP16,.25	-	SSOP16,.25	SOP16,.25	SOP16,.25	SSOP16,.25	-	SOP16,.25	SSOP16,.25
封装形状	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	-	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）	-	240	NOT SPECIFIED	NOT SPECIFIED	240	240	NOT SPECIFIED	260	240	240
电源	-	3.3/5 V	-	3.3/5 V	3.3/5 V	3.3/5 V	3.3/5 V	-	3.3/5 V	3.3/5 V
传播延迟（tpd）	-	0.7 ns	0.7 ns	0.7 ns	0.7 ns	0.7 ns	0.7 ns	0.7 ns	0.7 ns	0.7 ns
认证状态	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	-	0.25 ns	0.25 ns	0.25 ns	0.25 ns	0.25 ns	0.25 ns	0.25 ns	0.25 ns	0.25 ns
座面最大高度	-	1.75 mm	1.75 mm	1.75 mm	1.75 mm	1.75 mm	1.75 mm	1.75 mm	1.75 mm	1.75 mm
最大供电电压 (Vsup)	-	3.63 V	3.63 V	3.63 V	3.63 V	3.63 V	3.63 V	3.63 V	3.63 V	3.63 V
最小供电电压 (Vsup)	-	2.97 V	2.97 V	2.97 V	2.97 V	2.97 V	2.97 V	2.97 V	2.97 V	2.97 V
标称供电电压 (Vsup)	-	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	-	YES	YES	YES	YES	YES	YES	YES	YES	YES
温度等级	-	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	-	Tin/Lead (Sn85Pb15)	TIN LEAD	Tin/Lead (Sn85Pb15)	TIN LEAD	TIN LEAD	Tin/Lead (Sn85Pb15)	MATTE TIN	TIN LEAD	Tin/Lead (Sn85Pb15)
端子形式	-	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	-	0.635 mm	0.635 mm	0.635 mm	1.27 mm	1.27 mm	0.635 mm	0.635 mm	1.27 mm	0.635 mm
端子位置	-	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	-	20	NOT SPECIFIED	NOT SPECIFIED	20	30	NOT SPECIFIED	30	30	20
宽度	-	3.9 mm	3.9 mm	3.9 mm	3.9 mm	3.9 mm	3.9 mm	3.9 mm	3.9 mm	3.9 mm
最小 fmax	-	133 MHz	133 MHz	133 MHz	133 MHz	133 MHz	133 MHz	133 MHz	133 MHz	133 MHz
Base Number Matches	-	1	1	1	1	1	1	-	-	-

9112AM-17

9112AM-17概述

9112AM-17规格参数

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9112AM-17相似产品对比

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