COMMUNICATION SEMICONDUCTORS
MX614
Bell 202 Compatible Modem
PRELIMINARY INFORMATION
DATA BULLETIN
Features
•
•
•
•
1200bps - 1800bps half duplex Bell 202
Compatible Modem
Optional 1200bps Data Retiming Facility
can eliminate external UART
Optional 5bps and 150bps Back Channel
Optional Line Equalization
Applications
•
•
Low Voltage Operation (3.3V to 5.0V)
Low Power Operation
1mA typ. @ 3.3V Operating Mode
1µA typ. Zero-Power Mode
µ
•
•
Standard 3.58MHz Xtal/Clock
Telephone Telemetry Applications
Status
Telephone
Line
Line
Interface
Control
MX614
Data
µC
The MX614 is a low voltage, low power CMOS integrated circuit designed for the reception or transmission of
asynchronous 1200bps data. This device is compatible with Bell 202 type systems. The MX614 supports
5bps and 150bps 'back channel' operation. Asynchronous data rates up to 1818bps are also supported.
The MX614 provides an optional Tx and Rx data retiming function which can eliminate, based on user
preference, the need for a UART in the associated
µC
when operating at 1200bps. An optional line equalizer
has been incorporated into the receive path and is controlled by an external logic level.
The MX614 may be used in a wide range of telephone telemetry systems. A very low current “Zero Power
Mode (1µA typ.) and an operating current of 1mA typ. @ V
DD
= 3.3V, make the MX614 ideal for portable,
terminal and line powered applications. A standard 3.58MHz Xtal/Clock is required and the device operates
from a 3.0V to 5.5V supply.
The MX614 is available in 24-pin TSSOP (MX614TN), 16-pin SOIC (MX614DW) and 16-pin PDIP (MX614P)
packages.
2000 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480162.004
4800 Bethania Station Road, Winston-Salem, NC 27105 USA
All Trademarks and Service Marks are held by their respective companies.
Bell 202 Compatible Modem
2
MX614 PRELIMINARY INFORMATION
CONTENTS
Section
Page
1. Block Diagram ................................................................................................................. 3
2. Signal List........................................................................................................................ 4
3. External Components ..................................................................................................... 5
4. General Description ........................................................................................................ 6
4.1 Xtal Osc and Clock Dividers....................................................................................................6
4.2 Mode Control Logic .................................................................................................................6
4.3 Rx Input Amplifier....................................................................................................................6
4.4 Receive Filter and Equalizer ...................................................................................................6
4.5 Energy Detector ......................................................................................................................7
4.6 FSK Demodulator....................................................................................................................7
4.7 FSK Modulator and Transmit Filter .........................................................................................8
4.8 Rx Data Retiming ....................................................................................................................9
4.9 Tx Data Retiming ..................................................................................................................10
5. Application Notes.......................................................................................................... 12
5.1 Line Interface ........................................................................................................................12
6. Performance Specification........................................................................................... 13
6.1 Electrical Performance ..........................................................................................................13
6.2 Packaging .............................................................................................................................16
MX•COM, Inc. reserves the right to change specifications at any time and without notice.
2000 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480162.004
4800 Bethania Station Road, Winston-Salem, NC 27105 USA
All Trademarks and Service Marks are held by their respective companies.
Bell 202 Compatible Modem
3
MX614 PRELIMINARY INFORMATION
1. Block Diagram
XTAL/
CLOCK
XTAL
V
DD
V
BIAS
V
SS
RXAMPOUT
RXIN
Xtal Osc and
Clock Dividers
Energy
Detect
Mode
Control
Logic
Receive
Filter and
Equalizer
V
BIAS
FSK
De-modulator
Rx/Tx Data
Re-timing
Transmit Filter
and Output Buffer
FSK
Modulator
RXEQ
DET
M1
M0
RXD
CLK
RDY
TXD
TXOUT
Figure 1: Block Diagram
2000 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480162.004
4800 Bethania Station Road, Winston-Salem, NC 27105 USA
All Trademarks and Service Marks are held by their respective companies.
Bell 202 Compatible Modem
4
MX614 PRELIMINARY INFORMATION
2. Signal List
Pin No.
P, DW
1
2
3
4
5
6
7
8
9
TN
1
2
5
6
7
8
11
12
13
Signal
Name
XTAL
Description
Type
output
input
input
input
input
output
output
Power
output
Output of the on-chip Xtal oscillator inverter.
Input to the on-chip Xtal oscillator inverter.
A logic level input for setting the mode of the device. See
section 4.2
A logic level input for setting the mode of the device. See
section 4.2
Input to the Rx input amplifier.
Output of the Rx input amplifier
Output of the FSK generator.
Negative supply (ground).
Internally generated bias voltage, held at V
DD
/2 when the
device is not in 'Zero-Power' mode. Should be bypassed to
V
SS
by a capacitor mounted close to the device pins.
A logic level input for enabling/disabling the equalizer in the
receive filter. See section 4.4
A logic level input for either the raw input to the FSK
Modulator or data to be re-timed depending on the state of
the M0, M1 and CLK inputs. See section 4.9
A logic level input which may be used to clock data bits in or
out of the FSK Data Retiming block.
A logic level output carrying either the raw output of the FSK
Demodulator or re-timed characters depending on the state of
the M0, M1 and CLK inputs. See section 4.8
A logic level output of the on-chip Energy Detect circuit.
"Ready for data transfer" output of the on-chip data retiming
circuit. This open-drain active low output may be used as an
Interrupt Request/Wake-up input to the associated
µC.
An
external pull-up resistor should be connected between this
output and V
DD
.
Positive supply. Levels and thresholds within the device are
proportional to this voltage. Should be bypassed to V
SS
by a
capacitor mounted close to the device pins.
No internal connection
XTAL/CLOCK
M0
M1
RXIN
RXAMPOUT
TXOUT
V
SS
V
BIAS
10
11
14
17
RXEQ
TXD
input
input
12
13
18
19
CLK
RXD
input
output
14
15
20
23
DET
RDY
output
output
16
24
V
DD
Power
3, 4,
9, 10,
15,
16,
21,
22
N/C
2000 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480162.004
4800 Bethania Station Road, Winston-Salem, NC 27105 USA
All Trademarks and Service Marks are held by their respective companies.
Bell 202 Compatible Modem
5
MX614 PRELIMINARY INFORMATION
3. External Components
V
DD
C1
X1
C2
XTAL
1
2
3
4
5
6
7
8
16
15
14
V
DD
RDY
DET
RXD
CLK
TXD
RXEQ
V
BIAS
R1
C3
XTAL/CLOCK
M0
From µC
M1
RXIN
RXAMPOUT
TXOUT
V
SS
MX614
13
12
11
10
9
C4
R1
C1 C2
C3
C4
X1
Note 1
100kΩ
18pF
0.1µF
0.1µF
3.579545MHz
±5%
±10%
±10%
±10%
Figure 2: Recommended External Components for Typical Application
External Components Notes
1.
IMPORTANT:
This device is capable of detecting and decoding small amplitude signals. To achieve
this V
DD
and V
BIAS
decoupling and protecting the receive path from extraneous in-band signals are very
important. It is recommended that the decoupling capacitors be placed so that connections between
them and the device pins are as short as practicable e.g.
≤
1 inch from device pins. A ground plane
protecting the receive path will help attenuate interfering signals
2. A crystal frequency of 3.579545MHz
±0.1%
is required for correct FSK operation. For best results, a
crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of V
DD
peak-peak. Tuning fork crystals generally cannot meet this requirement. To obtain crystal oscillator
design assistance, consult your crystal manufacturer.
2000 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480162.004
4800 Bethania Station Road, Winston-Salem, NC 27105 USA
All Trademarks and Service Marks are held by their respective companies.
To/From µC
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
