BU-65142 and BUS-65142 SERIES
MIL-STD-1553 DUAL REDUNDANT
REMOTE TERMINAL HYBRID
DESCRIPTION
The BUS-65142 Series is a com-
plete dual redundant MIL-STD-
1553 Remote Terminal Unit (RTU)
packaged in a small 1.9" x 2.1"
hybrid. The device is based upon
two DDC custom ICs, which
includes two monolithic bi-polar low
power transceivers and one CMOS
protocol containing data buffers
and timing control logic. It supports
all 13 mode codes for dual redun-
dant operation, any combinaion of
which can be illegalized.
Parallel data transfers are accom-
plished with a DMA type handshak-
ing, compatible with most CPU
types. Data transfers to/from mem-
ory are simplified by the latched
command word and word count out-
puts.
Error detection and recovery are
enhanced by BUS-65142 Series
special features. A 14-bit built-in-
test word register stores RTU infor-
mation, and sends it to the Bus
Controller in response to the Mode
Command Transmit Bit Word. The
BUS-65142 Series performs contin-
uous on-line wraparound self-test,
and provides four error flags to the
host CPU. Inputs are provided for
host CPU control of 6 bits of the
RTU Status Word.
Its small hermetic package, -55°C
to +125°C operating temperature
range, and complete RTU operation
make the BUS-65142 ideal for most
MIL-STD-1553 applications requir-
ing hardware or microprocessor
subsystems.
FEATURES
•
Complete Intergrated Remote
Terminal Including:
–Dual Low-Power Transceivers
–Complete RT Protocol
•
Direct Interface to Systems With
No Processor
•
Radiation Tolerant Version
Available
•
Space Qualified Version
Available
•
High Reliability Screening
Available
DATA
BUS A
TRANSCEIVER
ENCODER/
DECODER
BIT
PROCESSOR
BUFFER
DB0-DB15
BUF ENA
DTREQ
DTGRT
DTACK
DTSTR
R/W
WATCHDOG
TIMEOUT
TRANSFER
CONTROLS
DATA
BUS B
TRANSCEIVER
ENCODER/
DECODER
BIT
PROCESSOR
CURRENT
WORD
COUNTER
PROTOCOL
SEQUENCER
AND
CONTROL
LOGIC
M
U
X
A0-A4
A5-A10
DAT/CMD
ILL CMD (ME)
SS REQ
ADBC
RT FLAG
SS BUSY
SS FLAG
MESS ERR
RT FAIL
HS FAIL
RTADD ERR
NBGT
INCMD
BITEN
STATEN
GBR
COMMAND
LATCH
RT ADDRESS
+
PARITY
STATUS
REGISTER
16 MHz CLOCK
ERROR FLAGS
TIMING FLAGS
DDC CUSTOM CHIP
FIGURE 1. BUS-65142 SERIES BLOCK DIAGRAM
©
1988, 1999 Data Device Corporation
TABLE 1. BU-65142 and BUS-65142/44 SPECIFICATIONS
PARAMETER
RECEIVER
Differential Input Impedance
(DC to 1 MHz)
Differential Input Voltage
Input Threshold Level
(Direct Coupled)
CMRR (DC to 2 MHz)
CMV (DC to 2 MHz)
TRANSMITTER
Differential Output Voltage
!
Direct Coupled Across 35
Ω,
Measured on Bus
!
Transformer Coupled Across 70
Ω,
Measured on Stub:
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, (Transformer
Coupled Across 70 ohms)
Rise/Fall Time
LOGIC
VIH
VIL
IIH (VIH=2.7V)
!
BRO ENA,
ADDRE-ADDRA(RTAD4-RTAD0),
ADDRP (connect to 30kΩ pull-up )
!
(VIH=2.7V) DB15 - DB0
TABLE 1. BU-65142 and BUS-65142/44 SPECIFICATIONS (continued)
UNITS
kohm
PARAMETER
LOGIC (continued)
VOH
!
(IOH=-2mA) DB15 - DB0
(connect to a 45kΩ pull-up )
C1 (f = 1 MHz)
C0 (f = 1 MHz)
CI0 ((f = 1 MHz)
!
DB15 - DB0
(connect to a 45kΩ pull-up )
POWER SUPPLY REQUIREMENTS
+5V (BU-65142X1/2,
BUS-65142/43/44/45)
Current Drain
-15V (BU-65142X1, BUS-65142/44)
Current Drain
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
-12V (BU-65142X2, BUS-65143/45)
Current Drain
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
POWER DISSIPATION (See Note)
Total Hybrid
!
BU-65142X1/BUS-65142/44
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-65142X2/BUS-65143/45
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
Hottest Die
!
BU-65142X1/BUS-65142/44
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
!
BU-65142X2/BUS-65143/45
MIN
4.0
TYP
MAX
MIN
TYP
MAX
UNITS
40
0.70
40
±10
1.20
Vp-p
Vp-p
dB
V
0.4
V
50
10
50
pF
pF
pF
6
18
7
21
9
27
10
Vp-p
Vp-p
mVp-p,
diff
mVp-p,
diff
nsec
V
4.5
50
-15.75
30
68
105
180
-12.6
30
80
130
230
5.5
115
-14.25
60
108
160
255
-11.4
60
120
185
305
V
mA
V
mA
mA
mA
mA
V
mA
mA
mA
mA
-250
100
2.4
150
+250
300
0.7
0.04
0.2
V
mA
0.04
0.2
±20
mA
µA
(connect to a 45kΩ pull-up )
!
(VIH≥2.4V) All Other Inputs
IIL (VIL=0.4V)
!
BRO ENA,
ADDRE-ADDRA(RTAD4-RTAD0),
ADDRP (connect to 30kΩ pull-up )
!
(VIL=0.4V) DB15 - DB0
(connect to a 45kΩ pull-up )
!
(VIL=≥0.7V) All Other Inputs---
VOH
!
(IOH=-0.4mA)
0.4
mA
0.700
0.912
1.125
1.550
0.610
0.860
1.110
1.160
1.475
1.856
2.238
3.000
1.295
1.680
2.065
2.895
W
W
W
W
W
W
W
W
0.4
±20
mA
µA
A9-A5(SA4-SA0), RTADERR,
HSFAIL, DAT/CMD, RTFAIL, BITEN,
NBGT, GBR, ME, STATEN
VOH
!
(IOH=-0.4mA) All Other Inputs---
VOH
!
(IOH=-0.4mA) DB15 - DB0
2.4
V
0.335
0.550
0.760
1.185
0.290
0.540
0.790
1.290
0.680
1.010
1.350
2.030
0.590
0.870
1.260
1.960
W
W
W
W
W
W
W
W
2.4
V
•
•
•
•
Idle
25% Transmitter Duty Cycle
50% Transmitter Duty Cycle
100% Transmitter Duty Cycle
2.4
V
(connect to a 45kΩ pull-up )
VOL
!
(IOH=-2mA)
A9-A5(SA4-SA0), RTADERR,
HSFAIL, DAT/CMD, RTFAIL, BITEN,
NBGT, GBR, ME, STATEN
VOH
!
(IOL=2 mA) All Other Inputs---
0.4
V
0.4
V
2
TABLE 1. BU-65142 and BUS-65142/44 SPECIFICATIONS (continued)
THERMAL
20
°C/W
• Thermal Resistance, Junction-to-
Case, Hottest Die (θJC)
-55
150
°C
• Operating Junction Temperature
-65
150
°C
• Storage Temperature
+300
°C
• Lead Temperature
(soldering, 10 sec.)
PHYSICAL CHARACTERISTICS
Size
78-pin Kovar (BUS-65142/43)
82-pin Kovar Flat Pack
(BUS-65142/43)
78-pin Ceramic QIP (BU-65142D)
INTRODUCTION
The BUS-65142 is a complete dual redundant Remote Terminal
Unit (RTU) packaged in a small 1.9 x 2.1 hybrid. It is fully com-
pliant with MIL-STD=1553B and supports all message formats.
As shown in FIGURE 1, it includes 2 transceivers and a custom
chip containing 2 encoders, 2 bit processors, an RTU protocol
sequencer and control logic, output latches, and buffers. With
the addition of 2 data bus transformers, the BUS-65142 is ready
for connection to a MIL-STD-1553 data bus.
Data is transferred to and from the subsystem host CPU over a
16-bit parallel highway, which is isolated by a set of bi-direction-
al buffers. All transfers are made with a DMA type handshake
sequence of request, grant and acknowledge. Read/write and
data strobes are provided to simplify interfacing to external
RAM. Also simplifying the RAM interface is the availability of
latched command word and auto-incrementing word counter.
These signals may be used as an address to map the data
directly to and from RAM.
The BUS-65142 allows the subsystem host CPU to control 6 of
the bits in the RTU status word. Of particular interest is the
Illegal Command input which may be used to set the message
error bit and illegalize any command word. The BUS-65142 pro-
vides four error flags to the subsystem host CPU for evaluating
its condition. In addition a continuous on-line self-test is per-
formed by the BUS-65142 on every transmission. The last
Transmitted Word of every message is wrapped around the
decoder and compared with the Actual Word. Any discrepancy
is flagged as an error.
1.87 x 2.10 x 0.25
(47.5 x 53.3 x 6.4)
1.61 x 2.20 x 0.181
(40.8 x 55.8 x 4.6)
1.80 x 2.10 x 0.21
(45.7 x 53.3 x 5.3)
1.80 x 2.10 x 0.21
(45.7 x 53.3 x 5.3)
in
(mm)
in
(mm)
in
(mm)
in
(mm)
78-pin Ceramic Flat Pack
(BU-65142F)
Weight
Note:
1.7
(4.1)
oz
(g)
Power dissipation specifications assume a transformer coupled
configuration, with external disipation (while transmitting) of
0.14 watts for the active isolation transformer, 0.8 watts for the
active coupling transformer, 0.45 watts for each of the two bus
isolation resistors, and 0.15 watts for each of the two bus termi-
nation resistors.
TIMING
TABLE 2. BU-65142 SERIES RADIATION SPECIFICATIONS
PART
NUMBER
TOTAL
DOSE
SINGLE EVENT
UPSET
SINGLE EVENT
LATCHUP
BU-65142
X1/X2
300K
Rad
5.3 x 10-6
errors/device-day,
(LET Threshold of
59 MeV/mg/cm2)
Immune
Interfacing the subsystem host CPU to the BUS-65142 is simple
and compatible with most microprocessors. FIGURE 3 and 4
illustrate typical MIL-STD-1553 messages for Transmit data and
Receive data. FIGURES 5 and 6 illustrate RT to RT transfers. In
each case
NBGT
identifies the start of the message, and
INCMD identifies that a command is being processed. The hand-
shake sequence
DTREQ
,
DTGRT
, and
DTACK
is used to trans-
feer each word over the parallel data highway.
DTSRB
and
RD / WR
are used to control transfers to RAM memory.
GBR
identifies a “good block received”, when a received message has
passed all validation checks and has the correct word count.
BUF ENA
(Buffer Enable) must be applied to enable the internal
tri-state buffers.
3
ERROR FLAGS
Four error flags are ouput to the subsystem to provide informa-
tion on the condition of the BUS-65142.
The
ME
(Message Error) line goes LOW if any of the fol-
lowing error conditions exist:
format error
word count error
invalid word
sync error
RT to RT address error
T/R bit error.
The
RTFAIL
(Remote Terminal Failure) line goes LOW
whenever the results of a continuous wraparound self-test
shows a discrepancy, or a transmitter watchdog timeout
has occurred.
The
HSFAIL
(Handshake Failure) line goes LOW whenev-
er the system dows not issue a
DTGRT
in response to a
DTREQ
before timing-out.
STATUS REGISTER
Six inputs to the BUS-65142 allow the subsystem host CPU to
control bits in the RTU status word. The Illegal Command input
may be used to set the Message Error bit in the Status Word and
suppress the transmission of data to the bus controller. This line
allows illegalization of any combination of commands. The
latched Command Word may be connected to the address pins
of an optional external PROM, which would drive the Illegal
Command line LOW when it identifies a command programmed
as illegal.
STATUS REGISTER BIT ASSIGNMENTS
The
SRQ
(Subsystem Request) line is used to set the
Status Word service request bit.
The
ADBC
(Accept Dynamic Bus Control) line is used to
set the Status Word bus control bit.
The
RTFLAG
(RT Flag Line) is used to set the Status Word
terminal flag bit.
The
BUSY
(Busy) line is used to set the Status Word busy
bit, and inhibit subsystem requests for data.
The
SSFLAG
(SubSystem Flag) line is used to set the
Status Word subsytem (fault) flag.
The
RTADR ERR
(RT Address Error) line goes LOW
whenever the sum of the 5 address lines and parity lines
show a parity error (the terminal will not respond to com-
mands while this error condition exists).
4
BUILT-IN-TEST
The BUS-65142 contains a 14-bit Built-In-Test (BIT) word regis-
ter which stores information about the condition of the RTU.
When a mode code is received to transmit the BIT word, the con-
tents of the BIT register is transmitted over the 1553 bus.
FIGURE 2 shows the fault assigned to each bit in the BIT word.
Conditions monitored are; transmitter timeouts, loop test failures,
transmitter shutdown, subsystem handshake failure, and the
results of individual message validations.
DATA SYNC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P
ALWAYS ZERO
{
CHANNEL A/B - TRANSMITTER TIMEOUT
CHANNEL B - TRANSMITTER TIMEOUT
HANDSHAKE FAILURE
CHANNEL A TRANSMITTER TIMEOUT
CHANNEL A/B - LOOP TEST FAILURE
CHANNEL B - LOOP TEST FAILURE
MODE CODE - T/R ERROR
CODE
{
ILLEGAL OR RESERVED MODEWITH MODE CODE
ILLEGAL USE OF BROADCAST
MESSAGE SERVICING ABORTED DUE TO LOW WORD COUNT
CHANNEL A - LOOP TEST FAILURE
CHANNEL B - TRANSMITTER SHUTDOWN
CHANNEL A - TRANSMITTER SHUTDOWN
MESSAGE SERVICING ABORTED DUE TO HIGH WORD COUNT
NON-MODE BROADCAST COMMAND TO TRANSMIT
NOTES
1. BITS 3-7 ARE CLEARED IN THE BEGINNING OF EACH NEW MESSAGE AND UPDATED AT THE END OF THE MESSAGE.
THEY ONLY REFLECT THE PRESENT COMMAND WORD.
2. BITS 0-2 AND 10-13 ARE LATCHED AND ONLY CLEARED BY A MODE RESET COMMAND OR A MASTER RESET (RESET).
3. BITS 8 AND 9 ARE SET ONLY BY THE MODE COMMAND FOR "TRANSMITTER SHUTDOWN" AND ARE CLEARED BY THE MODE COMMAND
FOR "OVERRIDE TRANSMITTER SHUTDOWN" OR "RESET REMOTE TERMINAL". BITS 8 AND 9 ARE ALSO CLEARED BY RESET.
FIGURE 2. BUILT-IN-TEST (BIT) WORD REGISTER
5
FPGA/CPLD
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