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IDT72V7280L15BB

产品描述FIFO, 16KX72, 10ns, Synchronous, CMOS, PBGA256, PLASTIC, FBGA-256
产品类别存储    存储   
文件大小443KB,共42页
制造商IDT (Integrated Device Technology)
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IDT72V7280L15BB概述

FIFO, 16KX72, 10ns, Synchronous, CMOS, PBGA256, PLASTIC, FBGA-256

IDT72V7280L15BB规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称IDT (Integrated Device Technology)
零件包装代码BGA
包装说明PLASTIC, FBGA-256
针数256
Reach Compliance Codenot_compliant
ECCN代码EAR99
最长访问时间10 ns
其他特性RETRANSMIT
最大时钟频率 (fCLK)66.7 MHz
周期时间15 ns
JESD-30 代码S-PBGA-B256
JESD-609代码e0
长度17 mm
内存密度1179648 bit
内存集成电路类型OTHER FIFO
内存宽度72
湿度敏感等级3
功能数量1
端子数量256
字数16384 words
字数代码16000
工作模式SYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织16KX72
可输出YES
封装主体材料PLASTIC/EPOXY
封装代码BGA
封装等效代码BGA256,16X16,40
封装形状SQUARE
封装形式GRID ARRAY
并行/串行PARALLEL
峰值回流温度(摄氏度)225
电源3.3 V
认证状态Not Qualified
座面最大高度3.5 mm
最大待机电流0.015 A
最大压摆率0.075 mA
最大供电电压 (Vsup)3.45 V
最小供电电压 (Vsup)3.15 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Lead (Sn63Pb37)
端子形式BALL
端子节距1 mm
端子位置BOTTOM
处于峰值回流温度下的最长时间30
宽度17 mm

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3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 72-BIT FIFO
512 x 72, 1,024 x 72
2,048 x 72, 4,096 x 72
8,192 x 72, 16,384 x 72
32,768 x 72, 65,536 x 72
IDT72V7230, IDT72V7240
IDT72V7250, IDT72V7260
IDT72V7270, IDT72V7280
IDT72V7290, IDT72V72100
FEATURES:
Choose among the following memory organizations:
IDT72V7230
512 x 72
IDT72V7240
1,024 x 72
IDT72V7250
2,048 x 72
IDT72V7260
4,096 x 72
IDT72V7270
8,192 x 72
IDT72V7280
16,384 x 72
IDT72V7290
32,768 x 72
IDT72V72100
65,536 x 72
100 MHz operation (10 ns read/write cycle time)
User selectable input and output port bus-sizing
- x72 in to x72 out
- x72 in to x36 out
- x72 in to x18 out
- x36 in to x72 out
- x18 in to x72 out
Big-Endian/Little-Endian user selectable word representation
Fixed, low first word latency
Zero latency retransmit
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Program programmable flags by either serial or parallel means
Select IDT Standard timing (using
EF
and
FF
flags) or First Word
Fall Through timing (using
OR
and
IR
flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
Asynchronous operation of Output Enable,
OE
Read Chip Select (
RCS
) on Read Side
Available in a 256-pin Fine Pitch Ball Grid Array package (PBGA)
Features JTAG (Boundary Scan)
High-performance submicron CMOS technology
Industrial temperature range (–40°C to +85°C) is available
°
°
FUNCTIONAL BLOCK DIAGRAM
D
0
-D
n
(x72, x36 or x18)
WEN
WCLK
LD
SEN
SCLK
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
WRITE CONTROL
LOGIC
WRITE POINTER
RAM ARRAY
512 x 72
1,024 x 72
2,048 x 72
4,096 x 72
8,192 x 72
16,384 x 72
32,768 x 72
65,536 x 72
FLAG
LOGIC
READ POINTER
BE
IP
BM
IW
OW
MRS
PRS
TCK
TRST
TMS
TDO
TDI
CONTROL
LOGIC
BUS
CONFIGURATION
RESET
LOGIC
JTAG
CONTROL
(BOUNDARY SCAN)
OUTPUT REGISTER
READ
CONTROL
LOGIC
RT
RM
RCLK
REN
RCS
Q
0
-Q
n
(x72, x36 or x18)
4680 drw01
OE
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DECEMBER 2003
DSC-4680/10

 
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