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70V3569S5DRGI8

产品描述Dual-Port SRAM, 16KX36, 5ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM, GREEN, PLASTIC, QFP-208
产品类别存储    存储   
文件大小181KB,共17页
制造商IDT (Integrated Device Technology)
下载文档 详细参数 选型对比 全文预览

70V3569S5DRGI8概述

Dual-Port SRAM, 16KX36, 5ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM, GREEN, PLASTIC, QFP-208

70V3569S5DRGI8规格参数

参数名称属性值
厂商名称IDT (Integrated Device Technology)
包装说明FQFP,
Reach Compliance Codecompliant
最长访问时间5 ns
其他特性PIPELINED OUTPUT MODE, SELF TIMED WRITE CYCLE
JESD-30 代码S-PQFP-G208
JESD-609代码e3
长度28 mm
内存密度589824 bit
内存集成电路类型DUAL-PORT SRAM
内存宽度36
功能数量1
端子数量208
字数16384 words
字数代码16000
工作模式SYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织16KX36
封装主体材料PLASTIC/EPOXY
封装代码FQFP
封装形状SQUARE
封装形式FLATPACK, FINE PITCH
并行/串行PARALLEL
座面最大高度4.1 mm
最大供电电压 (Vsup)3.45 V
最小供电电压 (Vsup)3.15 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层MATTE TIN
端子形式GULL WING
端子节距0.5 mm
端子位置QUAD
宽度28 mm

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HIGH-SPEED 3.3V 16K x 36
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
IDT70V3569S
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5ns (max)
Pipelined output mode
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
address inputs @ 133MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, single 3.3V (±150mV) power supply for
core
LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-ball fine-pitch Ball Grid Array, and 256-pin Ball
Grid Array
Green parts availble, see ordering instructions
Functional Block Diagram
BE
3L
BE
3R
BE
2L
BE
1L
BE
0L
BE
2R
BE
1R
BE
0R
R/W
L
B
W
0
L
B
W
1
L
B
W
2
L
B B
WW
3 3
L R
BB
WW
2 1
RR
B
W
0
R
R/W
R
CE
0L
CE
1L
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
OE
R
16K x 36
MEMORY
ARRAY
I/O
0L
- I/O
35L
Din_L
Din_R
I/O
0R
- I/O
35R
CLK
L
A
13L
A
0L
CNTRST
L
ADS
L
CNTEN
L
CLK
R
,
Counter/
Address
Reg.
A
13R
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0R
CNTRST
R
ADS
R
CNTEN
R
4831 tbl 01
OCTOBER 2014
1
©2014 Integrated Device Technology, Inc.
DSC 4831/13

70V3569S5DRGI8相似产品对比

70V3569S5DRGI8 70V3569S5BCGI8 70V3569S5DRG8 70V3569S4DRG8 70V3569S5BFGI8 70V3569S6DRG8 70V3569S5BCG8
描述 Dual-Port SRAM, 16KX36, 5ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM, GREEN, PLASTIC, QFP-208 Multi-Port SRAM, 16KX36, 5ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM, 1 MM PITCH, GREEN, BGA-256 Dual-Port SRAM, 16KX36, 5ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM, GREEN, PLASTIC, QFP-208 Dual-Port SRAM, 16KX36, 4.2ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM, GREEN, PLASTIC, QFP-208 Multi-Port SRAM, 16KX36, 5ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM, 0.80 MM PITCH, GREEN, FPBGA-208 Dual-Port SRAM, 16KX36, 6ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM, GREEN, PLASTIC, QFP-208 Multi-Port SRAM, 16KX36, 5ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM, 1 MM PITCH, GREEN, BGA-256
包装说明 FQFP, LBGA, BGA256,16X16,40 FQFP, FQFP, LFBGA, BGA208,17X17,32 FQFP, LBGA, BGA256,16X16,40
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant
最长访问时间 5 ns 5 ns 5 ns 4.2 ns 5 ns 6 ns 5 ns
其他特性 PIPELINED OUTPUT MODE, SELF TIMED WRITE CYCLE PIPELINED OUTPUT MODE, SELF TIMED WRITE CYCLE PIPELINED OUTPUT MODE, SELF TIMED WRITE CYCLE PIPELINED OUTPUT MODE, SELF TIMED WRITE CYCLE PIPELINED OUTPUT MODE, SELF TIMED WRITE CYCLE PIPELINED OUTPUT MODE, SELF TIMED WRITE CYCLE PIPELINED OUTPUT MODE, SELF TIMED WRITE CYCLE
JESD-30 代码 S-PQFP-G208 S-PBGA-B256 S-PQFP-G208 S-PQFP-G208 S-PBGA-B208 S-PQFP-G208 S-PBGA-B256
JESD-609代码 e3 e1 e3 e3 e1 e3 e1
长度 28 mm 17 mm 28 mm 28 mm 15 mm 28 mm 17 mm
内存密度 589824 bit 589824 bit 589824 bit 589824 bit 589824 bit 589824 bit 589824 bit
内存集成电路类型 DUAL-PORT SRAM MULTI-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM MULTI-PORT SRAM DUAL-PORT SRAM MULTI-PORT SRAM
内存宽度 36 36 36 36 36 36 36
功能数量 1 1 1 1 1 1 1
端子数量 208 256 208 208 208 208 256
字数 16384 words 16384 words 16384 words 16384 words 16384 words 16384 words 16384 words
字数代码 16000 16000 16000 16000 16000 16000 16000
工作模式 SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
最高工作温度 85 °C 85 °C 70 °C 70 °C 85 °C 70 °C 70 °C
组织 16KX36 16KX36 16KX36 16KX36 16KX36 16KX36 16KX36
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 FQFP LBGA FQFP FQFP LFBGA FQFP LBGA
封装形状 SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE
封装形式 FLATPACK, FINE PITCH GRID ARRAY, LOW PROFILE FLATPACK, FINE PITCH FLATPACK, FINE PITCH GRID ARRAY, LOW PROFILE, FINE PITCH FLATPACK, FINE PITCH GRID ARRAY, LOW PROFILE
并行/串行 PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
座面最大高度 4.1 mm 1.7 mm 4.1 mm 4.1 mm 1.7 mm 4.1 mm 1.7 mm
最大供电电压 (Vsup) 3.45 V 3.45 V 3.45 V 3.45 V 3.45 V 3.45 V 3.45 V
最小供电电压 (Vsup) 3.15 V 3.15 V 3.15 V 3.15 V 3.15 V 3.15 V 3.15 V
标称供电电压 (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
表面贴装 YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 INDUSTRIAL INDUSTRIAL COMMERCIAL COMMERCIAL INDUSTRIAL COMMERCIAL COMMERCIAL
端子面层 MATTE TIN Tin/Silver/Copper (Sn/Ag/Cu) MATTE TIN MATTE TIN Tin/Silver/Copper (Sn/Ag/Cu) MATTE TIN Tin/Silver/Copper (Sn/Ag/Cu)
端子形式 GULL WING BALL GULL WING GULL WING BALL GULL WING BALL
端子节距 0.5 mm 1 mm 0.5 mm 0.5 mm 0.8 mm 0.5 mm 1 mm
端子位置 QUAD BOTTOM QUAD QUAD BOTTOM QUAD BOTTOM
宽度 28 mm 17 mm 28 mm 28 mm 15 mm 28 mm 17 mm
厂商名称 IDT (Integrated Device Technology) IDT (Integrated Device Technology) - IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)

 
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