HIGH-SPEED 3.3V
128K x9/x8
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Features:
◆
◆
◆
◆
70V9199/099L
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 9ns (max.)
– Industrial: 9ns (max.)
Low-power operation
– IDT70V9199/099L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
Flow-Through or Pipelined output mode on either port via
the
FT/PIPE
pins
Dual chip enables allow for depth expansion without
additional logic
◆
◆
◆
◆
Counter enable and reset features
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 9 ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 15ns cycle time, 66 MHz operation in Pipelined output mode
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 100-pin Thin Quad Flatpack (TQFP)
Green parts available, see ordering information
Functional Block Diagram
R/W
L
OE
L
CE
0L
CE
1L
R/W
R
OE
R
CE
0R
CE
1R
1
0
0/1
1
0
0/1
FT/PIPE
L
0/1
1
0
0
1
0/1
FT/PIPE
R
I/O
0L
- I/O
8L(1)
I/O
0R
- I/O
8R(1)
I/O
Control
I/O
Control
.
A
16L
A
0L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
NOTE:
1. I/O
0X
- I/O
7X
for IDT70V9099.
A
16R
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
4859 drw 01
JULY 2019
1
©2019 Integrated Device Technology, Inc.
DSC-4859/9
70V9199/099L
High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70V9199/099 is a high-speed128K x9/x8 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold times.
The timing latitude provided by this approach allows systems to be
designed with very short cycle times.
With an input data register, the IDT70V9199/099 has been optimized
for applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by
CE
0
and CE
1,
permits the
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using CMOS high-performance technology, these devices
typically operate on only 500mW of power.
Pin Configuration
(1,2,3)
NC
NC
A
7R
A
8R
A
9R
A
10R
A
11R
A
12R
A
13R
A
14R
A
15R
A
16R
V
SS
NC
NC
NC
NC
CE
0R
CE
1R
CNTRST
R
R/W
R
OE
R
FT/PIPE
R
GND
NC
7574 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
76
49
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
48
47
46
45
44
43
42
41
NC
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
CNTEN
R
CLK
R
ADS
R
V
SS
V
SS
ADS
L
CLK
L
CNTEN
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
NC
NC
70V9199
PNG100
(4)
100-Pin TQFP
Top View
40
39
38
37
36
35
34
33
32
31
30
29
28
27
100
26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
NC
NC
I/O
8R
I/O
7R
I/O
6R
I/O
5R
I/O
4R
I/O
3R
V
DD
I/O
2R
I/O
1R
I/O
0R
V
SS
V
DD
I/O
0L
I/O
1L
V
SS
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
8L
V
SS
.
NC
NC
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
A
13L
A
14L
A
15L
A
16L
V
DD
NC
NC
NC
NC
CE
0L
CE
1L
CNTRST
L
R/W
L
OE
L
FT/PIPE
L
NC
NC
4859 drw 02
NOTES:
1. All V
DD
pins must be connected to power supply.
2. All V
SS
pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
6.42
2
70V9199/099L
High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration
(1,2,3)
(con't.)
NC
NC
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
CNTEN
R
CLK
R
ADS
R
V
SS
ADS
L
CLK
L
CNTEN
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
NC
NC
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
76
49
77
48
78
47
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
46
45
44
43
42
NC
NC
A
7R
A
8R
A
9R
A
10R
A
11R
A
12R
A
13R
A
14R
A
15R
A
16R
V
SS
NC
NC
NC
NC
CE
0R
CE
1R
CNTRST
R
R/W
R
OE
R
FT/PIPE
R
V
SS
NC
70V9099
PNG100
(4)
100-Pin TQFP
Top View
41
40
39
38
37
36
35
34
33
32
31
30
29
28
99
27
100
26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
NC
NC
NC
I/O
7R
I/O
6R
I/O
5R
I/O
4R
I/O
3R
V
DD
I/O
2R
I/O
1R
I/O
0R
V
SS
V
DD
I/O
0L
I/O
IL
V
SS
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
NC
V
SS
NC
NC
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
A
13L
A
14L
A
15L
A
16L
V
DD
NC
NC
NC
NC
CE
0L
CE
1L
CNTRST
L
R/W
L
OE
L
FT/PIPE
L
NC
NC
4859 drw 02a
NOTES:
1. All V
DD
pins must be connected to power supply.
2. All V
SS
pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
6.42
3
70V9199/099L
High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L,
CE
1L
R/W
L
OE
L
A
0L
- A
16L
I/O
0L
- I/O
8L
(1)
CLK
L
ADS
L
CNTEN
L
CNTRST
L
FT/PIPE
L
Right Port
CE
0R,
CE
1R
R/W
R
OE
R
A
0R
- A
16R
I/O
0R
- I/O
8R
(1)
CLK
R
ADS
R
CNTEN
R
CNTRST
R
FT/PIPE
R
V
DD
V
SS
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Address Strobe Enable
Counter Enable
Counter Reset
Flow-Through / Pipeline
Power (3.3V)
Ground (0V)
4859 tbl 01
NOTE:
1. I/O
0X
- I/O
7X
for IDT70V9099.
Truth Table I—Read/Write and Enable Control
(1,2,3)
OE
X
X
X
L
H
CLK
↑
↑
↑
↑
X
CE
0
H
X
L
L
L
CE
1
X
L
H
H
H
R/W
X
X
L
H
X
I/O
0-8
(4)
High-Z
High-Z
DATA
IN
DATA
OUT
High-Z
Deselected–Power Down
Deselected–Power Down
Write
Read
Outputs Disabled
4859 tbl 02
MODE
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, CNTRST
= X.
3.
OE
is an asynchronous input signal.
4. I/O
0
- I/O
7
for IDT70V9099.
Truth Table II—Address Counter Control
(1,2)
External
Address
X
An
An
X
Previous
Internal
Address
X
X
Ap
Ap
Internal
Address
Used
0
An
Ap
Ap + 1
MODE
CLK
↑
↑
↑
↑
ADS
X
L
(4)
H
H
CNTEN
X
X
H
L
(5)
CNTRST
L
(4)
H
H
H
I/O
(3)
D
I/O
(0)
D
I/O
(n)
D
I/O
(p)
D
I/O
(p+1)
Counter Reset to Address 0
External Address Loaded into Counter
External Address Blocked—Counter disabled (Ap reused)
Counter Enabled—Internal Address generation
4859 tbl 03
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
CE
0
and
OE
= V
IL
; CE
1
and R/W = V
IH
.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4.
ADS
and
CNTRST
are independent of all other signals including
CE
0
and CE
1
.
5. The address counter advances if
CNTEN
= V
IL
on the rising edge of CLK, regardless of all other signals including
CE
0
and CE
1
.
6.42
4
70V9199/099L
High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
(1)
Grade
Commercial
Industrial
Ambient
Temperature
(2)
0 C to +70 C
O
O
Recommended DC Operating
Conditions
Symbol
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
-0.3
(1)
Typ.
3.3
0
____
____
Max.
3.6
0
V
DD
+0.3V
(2)
0.8
Unit
V
V
V
V
4859 tbl 05
GND
0V
0V
V
DD
3.3V
+
0.3V
3.3V
+
0.3V
4859 tbl 04
V
DD
V
SS
V
IH
V
IL
-40 C to +85 C
O
O
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
NOTES:
1. V
IL
> -1.5V for pulse width less than 10 ns.
2. V
TERM
must not exceed V
DD
+0.3V.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect to
GND
Temperature
Under Bias
Storage
Temperature
Junction Temperature
DC Output Current
Commercial
& Industrial
-0.5 to +4.6
Unit
V
Capacitance
(1)
Symbol
C
IN
(T
A
= +25°C, f = 1.0MH
Z
)
Parameter
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
4859 tbl 07
T
BIAS
(3)
T
STG
T
JN
I
OUT
-55 to +125
-65 to +150
+150
50
o
C
C
C
C
OUT
(3)
o
o
mA
4859 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
DD
+0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
DD
+ 0.3V.
3. Ambient Temperature Under DC Bias. No AC Conditions. Chip deselect.
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. C
OUT
also references C
I/O
.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
DD
= 3.3V ± 0.3V)
70V9199/099L
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
V
DD
= 3.6V, V
IN
= 0V to V
DD
CE
= V
IH
or CE
1
= V
IL
, V
OUT
= 0V to V
DD
I
OL
= +4mA
I
OH
= -4mA
Test Conditions
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
4859 tbl 08
2.4
NOTE:
1. At V
DD
< 2.0V input leakages are undefined.
6.42
5
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