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SN54BCT8374A, SN74BCT8374A
SCAN TEST DEVICES
WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SCBS045E − JUNE 1990 − REVISED JULY 1996
D
Members of the Texas Instruments
D
D
D
D
D
D
D
SCOPE
Family of Testability Products
Octal Test-Integrated Circuits
Functionally Equivalent to ’F374 and
’BCT374 in the Normal-Function Mode
Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
Test Operation Synchronous to Test
Access Port (TAP)
Implement Optional Test Reset Signal by
Recognizing a Double-High-Level Voltage
(10 V ) on TMS Pin
SCOPE
Instruction Set
− IEEE Standard 1149.1-1990 Required
Instructions, Optional INTEST, CLAMP,
and HIGHZ
− Parallel-Signature Analysis at Inputs
− Pseudo-Random Pattern Generation
From Outputs
− Sample Inputs/ Toggle Outputs
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
SN54BCT8374A . . . JT PACKAGE
SN74BCT8374A . . . DW OR NT PACKAGE
(TOP VIEW)
CLK
1Q
2Q
3Q
4Q
GND
5Q
6Q
7Q
8Q
TDO
TMS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
1D
2D
3D
4D
5D
V
CC
6D
7D
8D
TDI
TCK
SN54BCT8374A . . . FK PACKAGE
(TOP VIEW)
description
The ’BCT8374A scan test devices with octal
edge-triggered D-type flip-flops are members of
the Texas Instruments SCOPE testability
integrated-circuit family. This family of devices
supports IEEE Standard 1149.1-1990 boundary
scan to facilitate testing of complex circuit-board
assemblies. Scan access to the test circuitry is
accomplished via the 4-wire test access port
(TAP) interface.
2D
1D
OE
NC
CLK
1Q
2Q
5
6
7
8
9
3D
4D
5D
NC
V
CC
6D
7D
4
3 2 1 28 27 26
25
24
23
22
21
20
10
11
19
12 13 14 15 16 17 18
8D
TDI
TCK
NC
TMS
TDO
8Q
NC − No internal connection
In the normal mode, these devices are functionally equivalent to the ’F374 and ’BCT374 octal D-type flip-flops.
The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device
terminals or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect
the functional operation of the SCOPE octal flip-flops.
In the test mode, the normal operation of the SCOPE octal flip-flops is inhibited and the test circuitry is enabled
to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform
boundary-scan test operations as described in IEEE Standard 1149.1-1990.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
3Q
4Q
GND
NC
5Q
6Q
7Q
Copyright
1996, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54BCT8374A, SN74BCT8374A
SCAN TEST DEVICES
WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SCBS045E − JUNE 1990 − REVISED JULY 1996
description (continued)
Four dedicated test terminals control the operation of the test circuitry: test data input (TDI), test data output
(TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing
functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation
(PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54BCT8374A is characterized for operation over the full military temperature range of −55°C to 125°C.
The SN74BCT8374A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(normal mode, each flip-flop)
INPUTS
OE
L
L
L
H
CLK
↑
↑
H or L
X
D
H
L
X
X
OUTPUT
Q
H
L
Q
0
Z
logic symbol
†
Φ
SCAN
’BCT8374A
TDI
TMS
TCK-IN
TCK-OUT
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
†
TDI
TMS
TCK
14
12
13
TDO
11
TDO
24
1
23
22
21
20
19
17
16
15
EN
C1
1D
2
3
4
5
7
8
9
10
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
SN54BCT8374A, SN74BCT8374A
SCAN TEST DEVICES
WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SCBS045E − JUNE 1990 − REVISED JULY 1996
functional block diagram
Boundary-Scan Register
V
CC
OE
24
V
CC
CLK
1
V
CC
1D
23
C1
1D
2
1Q
One of Eight Channels
Bypass Register
Boundary- Control
Register
V
CC
TDI
14
V
CC
TMS
12
V
CC
TCK
13
TAP
Controller
Instruction Register
V
CC
11
TDO
Pin numbers shown are for the DW, JT, and NT packages.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
3
SN54BCT8374A, SN74BCT8374A
SCAN TEST DEVICES
WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SCBS045E − JUNE 1990 − REVISED JULY 1996
Terminal Functions
TERMINAL
NAME
CLK
1D−8D
GND
OE
1Q−8Q
TCK
DESCRIPTION
Normal-function clock input. See function table for normal-mode logic. An internal pullup forces CLK to a high level if left
unconnected.
Normal-function data inputs. See function table for normal-mode logic. Internal pullups force these inputs to a high level if
left unconnected.
Ground
Normal-function output-enable input. See function table for normal-mode logic. An internal pullup forces OE to a high level
if left unconnected.
Normal-function data outputs. See function table for normal-mode logic.
Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to
TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pullup forces
TCK to a high level if left unconnected.
Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data through
the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.
Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register. An internal pullup forces TDO to a high level when it is not active
and is not driven from an external source.
Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP
controller states. An internal pullup forces TMS to a high level if left unconnected. TMS also provides the optional test reset
signal of IEEE Standard 1149.1-1990. This is implemented by recognizing a third logic level, double high (V
IHH
), at TMS.
Supply voltage
TDI
TDO
TMS
V
CC
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
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