August 1996
NDT410EL
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Power SOT N-Channel logic level enhancement mode
power field effect transistors are produced using
Fairchild's proprietary, high cell density, DMOS
technology. This very high density process is especially
tailored to minimize on-state resistance, provide superior
switching performance, and withstand high energy pulses
in the avalanche and commutation modes. These devices
are particularly suited for low voltage applications such as
automotive, DC/DC converters, PWM motor controls, and
other battery powered circuits where fast switching, low
in-line power loss, and resistance to transients are needed.
Features
2.1A 100V. R
DS(ON)
= 0.25
Ω
@ V
GS
= 5V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
___________________________________________________________________________________________
D
D
G
D
S
G
S
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C unless otherwise noted
Symbol
V
DSS
V
GSS
I
D
P
D
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
(Note 1a)
NDT410EL
100
20
2.1
10
3
1.3
1.1
-65 to 150
Units
V
V
A
W
T
J
,T
STG
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
42
12
°C/W
°C/W
* Order option J23Z for cropped center drain lead.
© 1997 Fairchild Semiconductor Corporation
NDT410EL Rev. B1
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE AVALANCHE RATINGS
(Note 2)
W
DSS
I
AR
Single Pulse Drain-Source Avalanche Energy V
DD
= 50 V, I
D
= 10A
Maximum Drain-Source Avalanche Current
15
10
mJ
A
OFF CHARACTERISTICS
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(ON)
I
D(on)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= 250 µA
V
DS
= 80 V, V
GS
= 0 V
T
J
= 55°C
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
V
GS
= 20 V, V
DS
= 0 V
V
GS
= -20 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= 250 µA
T
J
= 125°C
Static Drain-Source On-Resistance
V
GS
= 5 V, I
D
= 2.1 A
T
J
= 125°C
On-State Drain Current
Forward Transconductance
V
GS
= 5 V, V
DS
= 5 V
V
DS
= 10 V, I
D
= 2.1 A
V
DS
= 25 V, V
GS
= 0 V,
f = 1.0 MHz
10
6
1
0.65
1.5
1.1
0.2
0.37
100
1
10
100
-100
V
µA
µA
nA
nA
ON CHARACTERISTICS
(Note 2)
Gate Threshold Voltage
2
1.5
0.25
0.5
A
S
V
Ω
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
528
85
20
pF
pF
pF
SWITCHING CHARACTERISTICS
(Note 2)
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= 80 V, I
D
= 2.1 A, V
GS
= 5 V
V
DD
= 50 V, I
D
= 2.1 A,
V
GEN
= 5 V, R
GEN
= 25
Ω
9
72
49
47
20
120
80
80
16
ns
ns
ns
ns
nC
nC
nC
10
1.5
5.6
NDT410EL Rev. B1
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
2.3
(Note 2)
Units
A
V
ns
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
t
rr
Maximum Continuous Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
Reverse Recovery Time
V
GS
= 0 V, I
S
= 2.3 A
1.3
150
V
GS
= 0 V, I
S
= 2.3 A, dI
F
/dt = 100A/µs
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
T
−T
A
T
J
−T
P
D
(
t
) =
R
J
(t)
=
R
+R
A
(t)
=
I
2
(
t
) ×
R
DS(ON)@T
J
D
θJA
θJC
θCA
Typical R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 42
o
C/W when mounted on a 1 in
2
pad of 2oz copper.
b. 95
o
C/W when mounted on a 0.04 in
2
pad of 2oz copper.
c. 110
o
C/W when mounted on a 0.006 in
2
pad of 2oz copper.
1a
1b
1c
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDT410EL Rev. B1
Typical Electrical Characteristics
10
2
V
GS
= 10V
6.0
I
D
, DRAIN-SOURCE CURRENT (A)
8
4.0
3.5
DRAIN-SOURCE ON-RESISTANCE
5.0
R
DS(on)
, NORMALIZED
V
GS
= 3.0V
1.5
6
3.0
4
3.5
4.0
5.0
1
6.0
10
2
2.5
0
0
1
2
3
4
V
DS
, DRAIN-SOURCE VOLTAGE (V)
5
6
0.5
0
2
I
D
4
6
, DRAIN CURRENT (A)
8
10
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Gate Voltage and Drain Current.
2.5
3
I
DRAIN-SOURCE ON-RESISTANCE
2
D
= 2.1A
DRAIN-SOURCE ON-RESISTANCE
V
GS
= 5V
TJ = 125°C
2
V
GS
= 5V
R
DS(on)
, NORMALIZED
R
DS(ON)
, NORMALIZED
1.5
25°C
1
1
-55°C
0.5
-50
-25
0
25
50
75
100
125
T
J
, JUNCTION TEMPERATURE (°C)
150
175
0
0
2
I
D
4
6
, DRAIN CURRENT (A)
8
10
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On-Resistance Variation with Drain
Current and Temperature.
10
GATE-SOURCE THRESHOLD VOLTAGE (V)
1.2
V
DS
= 10V
8
I
D
, DRAIN CURRENT (A)
T
J
= -55°C 2 5
125
1.1
1
0.9
0.8
0.7
0.6
0.5
-50
V
DS
= V
GS
I
D
= 250
µ
A
6
4
2
0
1
2
V
GS
V
th
, NORMALIZED
3
4
, GATE TO SOURCE VOLTAGE (V)
5
-25
0
25
50
75
100
125
T , JUNCTION TEMPERATURE (°C)
J
150
175
Figure 5. Transfer Characteristics.
Figure 6. Gate Threshold Variation with
Temperature.
NDT410EL Rev. B1
Typical Electrical Characteristics
(continued)
DRAIN-SOURCE BREAKDOWN VOLTAGE (V)
1.15
10
I
D
= 250µA
1.1
I
S
, REVERSE DRAIN CURRENT (A)
5
V
GS
= 0V
BV
DSS
, NORMALIZED
1
0.5
TJ = 125°C
25°C
-55°C
1.05
1
0.1
0.05
0.95
0.9
-50
-25
0
T
J
25
50
75
100
125
, JUNCTION TEMPERATURE (°C)
150
175
0.01
0.4
V
SD
0.6
0.8
1
, BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 7. Breakdown Voltage Variation with
Temperature.
Figure 8. Body Diode Forward Voltage
Variation with Current and Temperature.
1300
1000
10
C iss
500
CAPACITANCE (pF)
300
200
V
GS
, GATE-SOURCE VOLTAGE (V)
8
I
D
= 2.1A
V
DS
= 20V
50V
80V
C oss
100
50
6
4
f = 1 MHz
V
GS
= 0 V
10
0.1
0.2
0.5
1
2
5
10
C rss
2
0
20
50
0
5
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
10
Q
g
, GATE CHARGE (nC)
15
20
Figure 9. Capacitance Characteristics.
Figure 10. Gate Charge Characteristics.
V
DD
t
d(on)
t
on
t
off
t
r
90%
t
d(off)
90%
t
f
V
IN
D
R
L
V
OUT
V
OUT
10%
V
GS
R
GEN
10%
INVERTED
G
DUT
90%
S
V
IN
10%
50%
50%
PULSE WIDTH
Figure 11. Switching Test Circuit.
Figure 12. Switching Waveforms.
NDT410EL Rev. B1
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