SS6383B(G)
3A
DDR
Termination Regulator
FEATURES
Source and sink current capability of
3A
Low output voltage offset, ±20mV
DESCRIPTION
The SS6383B linear regulator is designed to
provide
3A
source and sink current while
regulating an output voltage to within
45mV.
The SS6383B converts voltage supplies ranging
from 1.6V to 6V into an output voltage that
is set by two external voltage-divider resistors.
It provides an excellent voltage source for
active termination schemes for high-speed
transmission lines such as those seen in high-
speed memory buses.
The built-in current-limiting in source and sink
mode, together with thermal shutdown, provides
maximum protection to the SS6383B against
fault conditions.
High accuracy output voltage at full-load
V
OUT
adjustable by external resistors
Low external component count
Current limit protection
Thermal protection
SO-8,
TO-252-5 and TO-263-5
packages
APPLICATIONS
Mother Boards
Graphic Cards
DDR Termination Voltage Supply - supports
DDR1 (1.25V
TT
), DDR2 (0.9V
TT
), and meets
JEDEC SSTL-2 and SSTL-3 term. specifications
TYPICAL APPLICATION CIRCUIT
V
IN
=2.5V
+
C
IN
470µF
1
2
3
VIN
VOUT
GND
VCNTL
VREF
5
R1
100K
C
OUT
220µF
+
V
OUT
4
V
CNTL
=3.3V
+
C
CNTL
47µF
SS6383BCE5
R2
C1
100K
100pF
EN
SSM7002EN
This device is available with Pb-free lead finish (second-level interconnect) as SS6383BGxx
11/07/2004 Rev.2.01
www.SiliconStandard.com
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SS6383B(G)
ORDERING INFORMATION
SS6383BXXX
XX
Packing
TR: Tape
and reel
Package
type
CM5: TO-263-5, commercial
CE5 : TO-252-5, commercial
CS : SO-8, commercial
GM5 : TO-263-5, commercial, Pb-free
GE5 : TO-252-5, commercial, Pb-free
GS : SO-8, commercial, Pb-free
TO-263-5
FRONT VIEW
1: VIN
2: GND
3. VCNTL
4. VREF
5: VOUT
PIN CONFIGURATION
12345
TO-252-5
TOP VIEW
1: VIN
2: GND
3. VCNTL
4. VREF
5: VOUT
1234 5
Example:
SS6383BGE5TR
in TO-252-5
package,
with Pb-free lead finish,
shipped on tape and reel
SO-8
TOP VIEW
VIN 1
GND 2
VREF 3
VOUT 4
8 VCNTL
7 VCNTL
6 VCNTL
5 VCNTL
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Solder, 10sec)
Thermal Resistance
θ
JC
TO-263
TO-252
SO-8
Thermal Resistance
θ
JA
(Assume no ambient airflow, no heatsink)
TO-263
TO-252
SO-8
-0.4V to 7V
-40°C~85°C
-65°C ~150°C
260°C
3°C /W
12.5°C /W
40°C /W
60°C /W
100°C /W
160°C /W
Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.
11/07/2004 Rev.2.01
www.SiliconStandard.com
2 of 8
SS6383B(G)
TEST CIRCUIT
2.5
V
1
2
3
VIN
VOUT
GND
VREF
VCNTL
SS6383
B
4
5
V
OUT
+
1.
25V
C
OUT
10µF
3.3
V
ELECTRICAL CHARACTERISTICS
(V
CNTL
=3.3V, V
IN
=2.5V, V
REF
=0.5V
IN
, C
OUT
=10µF, T
A
=25°C, unless otherwise specified)
PARAMETER
Input Voltage (DDR1/2)
Output Voltage
Output Voltage Offset
Load Regulation (DDR1/2)
Quiescent Current
TEST CONDITIONS
Keep V
CNTL
≥V
IN
during
power on and off sequences
I
OUT
= 0mA
I
OUT
= 0mA
I
OUT
=0.1mA ~ +3A
I
OUT
=0.1mA ~ -3A
V
REF
<0.2V, V
OUT
= OFF
SYMBOL
V
IN
V
CNTL
V
OUT
V
OS
∆V
LOR
I
Q
I
CNTL
0
I
IL
3.2
4
-20
35
35
8
3
MIN.
1.6
3.0
TYP.
2.5
3.3
V
REF
20
45
mV
45
30
10
1
6.5
µA
mA
µA
A
MAX.
6
V
6
V
mV
UNIT
Operating Current of V
CNTL
No load
V
REF
Bias Current
Current Limit
THERMAL PROTECTION
Thermal Shutdown
Temperature
Thermal Shutdown
Hysteresis
3.3V≤V
CNTL
≤5V
Guaranteed by design
V
REF
=1.25V
T
SD
125
150
°C
°C
30
SHUTDOWN SPECIFICATIONS
Shutdown Threshold
Output ON (V
REF
=0V 1.25V)
Output OFF (V
REF
=1.25V 0V)
0.8
V
0.2
Note 2: V
OS
is the voltage measurement, which is defined as
the difference between
V
OUT
and
V
REF.
Note 3: Load regulation is measured at constant junction temperature, using pulse testing with a low ON time.
Note 4: Current limit is measured by pulsing a short time.
Note 5:
To
operate
the
system safely; V
CNTL
must be always greater than V
IN
.
Note 6: Specifications are guaranteed by Statistical Quality Controls (SQC),
and
not production tested,
within
the
operating temperature range
of
-40°C to 85°C.
Note
7:
DDR2 is not
supported in the
TO-263 package.
11/07/2004 Rev.2.01
www.SiliconStandard.com
3 of 8
SS6383B(G)
TYPICAL PERFORMANCE CHARACTERISTICS
0.52
Threshold Voltage (V)
Threshold Voltage (V)
V
CNTL
=3.3V
V
IN
=2.5V
0.52
V
CNTL
=5V
0.48
0.44
0.40
0.36
0.32
0.48
0.44
0.40
0.36
0.32
V
IN
=2.5V
-20
0
Temperature
(
°C)
20
40
60
80
100
120
40
20
0
20
40
60
80
100
120
Fig. 1 Turn-On Threshold vs. Temp.
Temperature (
°C)
Fig. 2 Turn On Threshold vs. Temp.
6
Output Voltage Offset (mV)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-40
Sourcing Current (A)
V
CNTL
=3.3V
V
IN
=2.5V
V
REF
=1.25V
No Load
5
V
CNTL
=3.3V
V
IN
=2.5V
V
REF
=1.25V
4
3
-20
0
20
40
60
80
100
120
2
-40
-20
0
20
40
60
80
100
120
Temperature (
°C)
Fig. 3 Output Voltage Offset vs. Temp.
Temperature (
°C)
Fig. 4 Current-Limit (Sourcing) vs. Temp.
6
Sinking Current (A)
5
V
CNTL
=3.3V
V
IN
=2.5V
V
REF
=1.25V
V
CNTL
=3.3V
V
IN
=2.5V, V
REF
=1.25V
4
V
OUT
, 50mV/div
I
OUT
,
2A/div
3
2
-40
-20
0
20
40
60
80
100
120
Temperature (
°C)
Fig. 5 Current-Limit (Sinking) vs. Temp.
Fig. 6 Transient Response at 1.25V
TT
/3A
11/07/2004 Rev.2.01
www.SiliconStandard.com
4 of 8
SS6383B(G)
TYPICAL PERFORMANCE CHARACTERISTICS
(Continued)
V
CNTL
=3.3V
V
IN
=2.5V
V
REF
=1.25V
V
CNTL
=3.3V
V
IN
=2.5V
V
REF
=1.25V
Iout, 2A/div
Iout, 2A/div
Fig. 7 Output Short-Circuit Protection (Sinking)
Fig. 8 Output Short-Circuit Protection (Sourcing)
BLOCK DIAGRAM
VCNTL
VIN
+
Control
VREF
VOUT
-
Current
Limit
Thermal
Shutdown
VOUT
Shutdown
GND
11/07/2004 Rev.2.01
www.SiliconStandard.com
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