128K x 32 SRAM Module
PUMA 2/67/77S4000/A-020/025/35
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (001) 858 674 2233, Fax No: (001) 858 674 2230
Issue 4.3 : December 1999
Description
Features
4 Megabit SRAM module.
Fast Access Times of 20/25/35 ns.
Output Configurable as 32 / 16 / 8 bit wide.
Upgradeable footprint.
Operating Power 3740 / 2310 / 1595 mW (Max).
Low Power Standby (L version) 220 mW (Max).
3.0V Battery Back-up Capability.
TTL Compatible Inputs and Outputs.
May be screened in accordance with MIL-STD-883.
PUMA 2 - 66 pin ceramic PGA.
PUMA 67 - 68 pin ceramic JLCC.
PUMA 77 - 68 pin ceramic Gullwing.
Available in PGA (PUMA 2), JLCC (PUMA 67) and
•
Gullwing (PUMA 77) footprints. The PUMA **S4000
•
is a 4 Mbit SRAM module, user configurable as
•
128K x 32, 256K x 16 or 512K x 8. The device is
•
available with fast access times of 20, 25 and 30ns.
•
A low power standby and Data Retention mode is
available. The device may be screened in
•
accordance with MIL-STD-883C.
•
•
•
•
•
Block Diagram
PUMA 2S4000, 67S4000A and 77S4000A
A0~A16
OE
WE4
WE3
WE2
WE1
128Kx8
SRAM
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
128Kx8
SRAM
128Kx8
SRAM
128Kx8
SRAM
Block Diagram
PUMA 67S4000 and 77S4000
A0-A16
OE
WE
128Kx8
SRAM
CS1
CS2
CS3
CS4
D0-7
D8-15
D16-23
D24-31
128Kx8
SRAM
128Kx8
SRAM
128Kx8
SRAM
Pin Functions
A0~A16
CS1~4
OE
GND
Address Input
Chip Select
Output Enable
Ground
D0~D31
WE1~4
Vcc
Data Inputs/Outputs
Write Enables
Power (+5V)
PUMA 2/67/77S4000/A - 020/025/35
Issue 4.3 : December 1999
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Voltage on any pin relative to GND
(2)
Power Dissipation
Storage Temperature
V
T
P
T
T
STG
-0.5V to +7.0
4
-65 to +150
V
W
°
C
Notes (1) Stresses above those listed may cause permanent damage. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
(2) Pulse width: -3.0V for less than 10ns.
Recommended Operating Conditions
min
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
V
CC
V
IH
V
IL
T
A
T
AI
T
AM
4.5
2.2
-0.5
0
-40
-55
typ
5.0
-
-
-
-
-
max
5.5
6.0
0.8
70
85
125
V
V
V
°
C
°
C (Suffix
I)
°
C (Suffix
M, MB)
DC Electrical Characteristics
(V
CC
=5V±10%,T
A
=-55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
32 bit
16 bit
8 bit
Standby Supply Current
Output Voltage Low
Output Voltage High
(TTL)
-L Version
Symbol Test Condition
I
LI1
I
LO
I
CC32
I
CC16
I
CC8
I
SB1
I
SB2
V
OL
V
OH
V
IN
=0V to V
CC
CS
(1)
=V
IH
or OE=V
IH
, V
I/O
=0V to V
CC
WE=V
IL
Min cycle,duty=100%,I
I/O
=0mA,CS=V
IL
As above
Min cycle,duty=100%,I
I/O
=0mA,CS=V
IL
CS
(1)
≥V
IH
V
CC
= 5.5V
CS
(1)
≥
V
IH
, V
IL
≤
V
IN
≥
V
IH,
f = 0 Hz
I
OL
= 8.0mA
I
OH
= -4.0mA
min
-8
-8
-
-
-
-
-
-
2.4
typ
-
-
-
-
-
-
-
-
-
max Unit
8
8
µA
µA
680 mA
420 mA
290 mA
160 mA
40
0.4
-
mA
V
V
Notes: (1) CS and WE above are accessed through CS1~4 and WE1~4 respectively. These inputs must be
operated simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode.
Capacitance
(V
CC
=5V±10%,T
A
=25°C)
Note: (1) On the standard module, WE = 30 pF max.
Parameter
Input Capacitance Address, OE
WE1~4
(1)
, CS1~4
I/O Capacitance
D0~D31
Symbol
C
IN1
C
IN2
C
I/O
Test Condition
V
IN
=0V
V
IN
=0V
V
I/O
=0V
typ
-
-
-
max Unit
30
16
30
pF
pF
pF (8 bit mode)
These parameters are calculated, not measured.
2
PUMA 2/67/77S4000/A - 020/025/35
Issue 4.3 : December 1999
Operating Modes
The table below shows the logic inputs required to control the operating modes of each of the SRAMs on the
modules.
Mode
Not Selected
Output Disable
Read
Write
1 = V
IH
,
0 = V
IL
,
X = Don't Care
CS
1
0
0
0
OE
X
1
0
X
WE
X
1
1
0
V
CC
Current
I
SB1
,I
SB2
I
CC
I
CC
I
CC
I/O Pin
High Z
High Z
D
OUT
D
IN
Reference Cycle
Power Down
-
Read Cycle
Write Cycle
Note: CS above is accessed through CS1~4 (and WE by WE1~4 on the PUMA 2S4000, 67S4000A, 77S4000A). For correct
operation, CS1~ 4 (and WE1~4) must operate simultaneously for 32 bit operation, in pairs for 16 bit operation, or
singly for 8 bit operation.
AC Test Conditions
*Input pulse levels: 0.0V to 3.0V
*Input rise and fall times: 3 ns
*Input and Output timing reference levels: 1.5V
*V
cc
=5V±10%
*PUMA module is tested in 32 bit mode.
Output Load
I/O Pin
166
Ω
1.76V
30pF
Low V
cc
Data Retention Characteristics - L Version Only
(T
A
=-55°C to +125
o
C)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention
Operation Recovery Time
Symbol Test Condition
V
DR
I
CCDR
t
CDR
t
R
CS1~4
≥
V
CC
-0.2V
V
CC
= 3.0V, CS1~4
≥
V
CC
-0.2V,
V
IN
≥
V
CC
-0.2V or
≤
0.2V
See Retention Waveform
See Retention Waveform
min
2
-
-
-
typ
-
-
-
-
max
-
20
-
-
Unit
V
mA
ns
ns
3
PUMA 2/67/77S4000/A - 020/025/35
Issue 4.3 : December 1999
AC OPERATING CONDITIONS
Read Cycle
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Output Disable to Output in High Z
(3)
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
OHZ
020
min
max
20
-
-
-
5
6
0
0
0
-
20
20
9
-
-
-
9
9
025
min
max
25
-
-
-
5
5
0
-
-
-
25
25
8
-
-
-
15
15
min
35
-
-
-
5
5
0
-
-
35
max Units
-
35
35
12
-
-
-
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Deselection to Output in High Z
(3)
t
CHZ
Write Cycle
020
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Output Active from End of Write
Data Hold from Write Time
Write to Output High Z
025
max
-
-
-
-
-
-
15
-
-
-
35
max
-
-
-
-
-
-
-
-
-
10
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
DW
t
OW
t
DH
t
WHZ
min
20
15
15
0
15
0
0
15
2*
5
min
25
16
16
0
15
5
10
3
2*
0
min
35
20
20
0
20
5
15
3
2*
0
max
-
-
-
-
-
-
-
-
-
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* Note : Only applies to PUMA 67S4000/A otherwise t
DH
(min) = 0
4
PUMA 2/67/77S4000/A - 020/025/35
Issue 4.3 : December 1999
Read Cycle Timing Waveform
(1,2)
t
A0~A16
RC
t
AA
OE
t
OE
t
OLZ
CS1~4
t
OH
t
CLZ
t
ACS
t
CHZ(3)
t
OHZ(3)
High-Z
D0~31
Data Valid
Notes:
(1) During the Read Cycle, WE is high for the modules.
(2) Address valid prior to or coincident with CS transition Low.
(3) t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels. These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
t
WC
A0~A16
OE
t
AS(3)
t
AW
t
CW(4)
(6)
t
WR
(2)
CS1~4
t
WP(1)
WE1~4
t
OHZ(3,9)
D0~31out
High-Z
t
DW
High-Z
t
OW
t
DH
D0~31in
5
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