DRAM MODULE
M53640812CW0/CB0
M53640812CW0/CB0 with EDO Mode
8M x 36 DRAM SIMM using 4Mx4 EDO and 4Mx4 Quad CAS, 2K Refresh, 5V
GENERAL DESCRIPTION
The Samsung M53640812C is a 8Mx36bits Dynamic RAM
high density memory module. The Samsung M53640812C
consists of sixteen CMOS 4Mx4bits DRAMs in 24-pin SOJ
package and two CMOS 4Mx4 bit Quad CAS with EDO DRAM
in 28-pin SOJ package mounted on a 72-pin glass-epoxy sub-
strate. A 0.1 or 0.22uF decoupling capacitor is mounted on the
printed circuit board for each DRAM. The M53640812C is a
Single In-line Memory Module with edge connections and is
intended for mounting into 72 pin edge connector sockets.
FEATURES
• Part Identification
- M53640812CW0(2048 cycles/32ms Ref, SOJ, Solder)
- M53640812CB0(2048 cycles/32ms Ref, SOJ, Gold)
• Fast Page Mode with Extended Data Out
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• TTL compatible inputs and outputs
• Single +5V±10% power supply
• JEDEC standard PDPin & pinout
• PCB : Height(1000mil), double sided component
PERFORMANCE RANGE
Speed
-C50
-C60
t
RAC
50ns
60ns
t
CAC
13ns
15ns
t
RC
90ns
110ns
t
HPC
25ns
30ns
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Symbol
V
SS
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
A11
Vcc
A8
A9
RAS1
RAS0
DQ26
DQ8
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Symbol
DQ17
DQ35
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1
NC
W
NC
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
Vcc
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
PD1
PD2
PD3
PD4
NC
Vss
PIN NAMES
Pin Name
A0 - A10
DQ0 - DQ35
W
RAS0, RAS1
CAS0 - CAS3
PD1 -PD4
Vcc
Vss
NC
Function
Address Inputs(2K Ref)
Data In/Out
Read/Write Enable
Row Address Strobe
Column Address Strobe
Presence Detect
Power(+5V)
Ground
No Connection
PRESENCE DETECT PINS (Optional)
Pin
PD1
PD2
PD3
PD4
50NS
NC
Vss
Vss
Vss
60NS
NC
Vss
NC
NC
* Pin connection changing available
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
CAS0
RAS0
CAS
RAS
OE
U0
W
A0-A10
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0-DQ3
M53640812CW0/CB0
DQ0
U9
DQ1
DQ2
DQ3A0-A10
W
DQ0
U10
DQ1
DQ2
DQ3 A0-A10 W
DQ0
U11
DQ1
DQ2
DQ3 A0-A10 W
DQ0
U12
DQ1
DQ2
DQ3 A0-A10 W
DQ0
U13
DQ1
DQ2
DQ3 A0-A10 W
DQ0
U14
DQ1
DQ2
DQ3 A0-A10 W
DQ0
U15
DQ1
DQ2
DQ3 A0-A10 W
DQ0
U16
DQ1
DQ2
DQ3 A0-A10 W
CAS
RAS
OE
CAS0
RAS1
DQ4-DQ7
CAS
RAS
OE
U1
W
A0-A10
CAS
RAS
OE
DQ9-DQ12
CAS1
CAS
RAS
OE
U2
W
A0-A10
CAS
RAS
OE
CAS1
DQ13-DQ16
CAS
RAS
OE
U3
W
A0-A10
U4
W
A0-A10
U5
W
A0-A10
CAS
RAS
OE
DQ18-DQ21
CAS2
CAS
RAS
OE
CAS
RAS
OE
CAS2
DQ22-DQ25
CAS
RAS
OE
CAS
RAS
OE
DQ27-DQ30
CAS3
CAS
RAS
OE
U6
W
A0-A10
CAS
RAS
OE
CAS3
DQ31-DQ34
CAS
RAS
OE
U7
W
A0-A10
CAS
RAS
OE
CAS0
CAS1
CAS2
CAS3
RAS
OE W
W
A0-A10
Vcc
U8
DQ0
DQ1
DQ2
DQ3
DQ8
DQ17
DQ26
DQ35
A0-A10
CAS0
U17
CAS1
DQ1
CAS2
DQ2
CAS3
DQ3
RAS
OE
A0-A10 W
DQ0
.1 or .22uF Capacitor
for each DRAM
Vss
To all DRAMs
DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
IN
, V
OUT
V
CC
T
stg
P
d
I
OS
M53640812CW0/CB0
Rating
-1 to +7.0
-1 to +7.0
-55 to +150
18
50
Unit
V
V
°C
W
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70°C)
Item
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
*1 : V
CC
+2.0V/20ns, Pulse width is measured at V
CC
.
*2 : -2.0V/20ns, Pulse width is measured at V
SS
.
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.4
-1.0
*2
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+1
*1
0.8
Unit
V
V
V
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Symbol
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
I(L)
I
O(L)
V
OH
V
OL
Speed
-C50
-C60
Don′t care
-C50
-C60
-C50
-C60
Don′t care
-C50
-C60
Don′t care
Don′t care
M53640812CW0/CB0
Min
-
-
Max
1008
918
36
1008
918
828
738
18
1008
918
90
10
-
0.4
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
uA
V
V
-
-
-
-
-
-
-
-
-90
-10
2.4
-
I
CC1
: Operating Current * (RAS, CAS, Address cycling @
t
RC
=min)
I
CC2
: Standby Current (RAS=CAS=W=V
IH
)
I
CC3
: RAS Only Refresh Current * (CAS=V
IH
, RAS cycling @
t
RC
=min)
I
CC4
: EDO Mode Current * (RAS=V
IL
, CAS Address cycling :
t
HPC
=min)
I
CC5
: Standby Current (RAS=CAS=W=Vcc-0.2V)
I
CC6
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @
t
RC
=min)
I
I(L)
: Input Leakage Current (Any input 0≤V
IN
≤Vcc+0.5V,
all other pins not under test=0 V)
I
O(L)
: Output Leakage Current(Data Out is disabled, 0V≤V
OUT
≤Vcc)
V
OH
: Output High Voltage Level (I
OH
= -5mA)
V
OL
: Output Low Voltage Level (I
OL
= 4.2mA)
* NOTE
: I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one EDO mode cycle,
t
HPC
.
DRAM MODULE
CAPACITANCE
(T
A
= 25°C, V
CC
=5V, f = 1MHz)
Item
Input capacitance[A0-A10]
Input capacitance[W]
Input capacitance[RAS0, RAS1]
Input capacitance[CAS0 - CAS3]
Input/Output capacitance[DQ0-35]
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
DQ1
Min
-
-
-
-
-
M53640812CW0/CB0
Max
110
130
80
40
25
Unit
pF
pF
pF
pF
pF
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
V
CC
=5.0V±10%. See notes 1,2.)
Test condition : V
ih
/V
il
=2.4/0.8V, V
oh
/V
ol
=2.0/0.8V, Output loading CL=100pF
Parameter
Random read or write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay from CAS
Transition time(rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in set-up time
Data-in hold time
Refresh period (2K Ref)
Write command set-up time
CAS setup time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS to CAS precharge time
Symbol
-C50
Min
90
50
13
25
3
3
2
30
50
13
38
8
20
15
5
0
10
0
8
25
0
0
0
10
10
13
8
0
32
0
5
10
5
0
5
10
5
10K
37
25
10K
13
50
3
3
2
40
60
15
45
10
20
15
5
0
10
0
10
30
0
0
0
10
10
15
10
0
10
32
10K
45
30
10K
15
50
Max
Min
110
60
15
30
-C60
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
7
9
9
8
8
13
4
10
3,4,10
3,4,5
3,10
3
6,11,12
2
Note
t
RC
t
RAC
t
CAC
t
AA
t
CLZ
t
CEZ
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
REF
t
WCS
t
CSR
t
CHR
t
RPC
DRAM MODULE
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
V
CC
=5.0V±10%. See notes 1,2.)
Test condition : V
ih
/V
il
=2.4/0.8V, V
oh
/V
ol
=2.0/0.8V, Output loading CL=100pF
Parameter
CAS precharge time (C-B-R counter test cycle)
Access time from CAS precharge
Hyper page mode cycle time
CAS precharge time(Hyper page cycle)
RAS pulse width(Hyper page cycle)
RAS hold time from CAS precharge
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
Output data hold time
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
W pulse width (Hyper Page Cycle)
Hold time CAS low to CAS high
Symbol
-C50
Min
20
30
25
8
50
30
10
10
5
3
3
15
5
5
13
13
200K
Max
M53640812CW0/CB0
-C60
Min
20
35
30
10
60
35
10
10
5
3
3
15
5
5
15
15
200K
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
t
CPT
t
CPA
t
HPC
t
CP
t
RASP
t
RHCP
t
WRP
t
WRH
t
DOH
t
REZ
t
WEZ
t
WED
t
WPE
t
CLCH
3
13
6,11,12
6,11
14
NOTES
1. An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
2. V
IH
(min) and V
IL
(max) are reference levels for measuring
timing of input signals. Transition times are measured
between V
IH
(min) and V
IL
(max) and are assumed to be 5ns
for all inputs.
3. Measured with a load equivalent to 2 TTL loads and 100pF.
4. Operation within the
t
RCD
(max) limit insures that
t
RAC
(max)
can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then
access time is controlled exclusively by
t
CAC
.
5. Assumes that
t
RCD
≥
t
RCD
(max).
6. This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V
OH
or
V
OL
.
7.
t
WCS
is non-restrictive operating parameter. It is included in
the data sheet as electrical characteristics only. If
t
WCS
≥
t
WCS
(min), the cycle is an early write cycle and the data
out pin will remain high impedance for the duration of the
cycle.
8. Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
9. These parameter are referenced to the CAS leading edge in
early write cycles and to the W leading edge in read-write
cycles.
10. Operation within the
t
RAD
(max) limit insures that
t
RAC
(max)
can be met.
t
RAD
(max) is specified as reference point only. If
t
RAD
is greater than the specified
t
RAD
(max) limit, then
access time is controlled by
t
AA
.
11.
t
CEZ
(max),
t
REZ
(max),
t
WEZ
(max) and
t
OEZ
(max) define the
time at which the output achieves the open circuit condition
and are not referenced to output voltage level.
12. If RAS goes to high before CAS high going, the open circuit
condtion of the output is achieved by CAS high going. If CAS
goes to high before RAS high going, the open circuit condtion
of the output is achieved by RAS high going.
13.
t
ASC
≥
t
CP
min
14. In order to hold the address latched by the first CAS going
low, the parameter
t
CLCH
must be met.
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