CAT93C46/56/57/66/86
1K/2K/2K/4K/16K-Bit Microwire Serial EEPROM
FEATURES
s
High speed operation:
H
LOGEN
FR
A
EE
LE
A
D
F
R
E
E
TM
s
Power-up inadvertant write protection
s
1,000,000 Program/erase cycles
s
100 year data retention
s
Commercial, industrial and automotive
– 93C46/56/57/66: 1MHz
– 93C86: 3MHz
s
Low power CMOS technology
s
1.8 to 6.0 volt operation
s
Selectable x8 or x16 memory organization
s
Self-timed write cycle with auto-clear
s
Hardware and software write protection
temperature ranges
s
Sequential read (except CAT93C46)
s
Program enable (PE) pin (CAT93C86 only)
s
“Green” package option available
DESCRIPTION
The CAT93C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit
Serial EEPROM memory devices which are configured
as either registers of 16 bits (ORG pin at V
CC
) or 8 bits
(ORG pin at GND). Each register can be written (or read)
serially by using the DI (or DO) pin. The CAT93C46/56/
57/66/86 are manufactured using Catalyst’s advanced
CMOS EEPROM floating gate technology. The devices
are designed to endure 1,000,000 program/erase cycles
and have a data retention of 100 years. The devices are
available in 8-pin DIP, 8-pin SOIC, 8-pin TSSOP and 8-
pad TDFN packages.
PIN CONFIGURATION
DIP Package (P, L)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
SOIC Package (J,W) SOIC Package (S,V) SOIC Package (K,X)
1
2
3
4
8
7
6
5
ORG
GND
DO
DI
CS
SK
DI
DO
1
2
3
4
8
7
6
5
CS
NC (PE*) SK
ORG
DI
GND
DO
VCC
1
2
3
4
8
7
6
5
VCC
NC (PE*)
ORG
GND
TSSOP Package (U,Y)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
VCC
NC (PE*)
NC (PE*)
VCC
ORG
CS
SK
GND
*Only For 93C86
** TSSOP (U/Y) package only available for 93C46/56/57/66
TDFN Package (RD4, ZD4)
VCC
8
NC
7
ORG
6
GND
5
CAT93C46
CAT93C56
CAT93C66
PIN FUNCTIONS
Pin Name
CS
SK
DI
DO
V
CC
GND
ORG
NC
PE*
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
+1.8 to 6.0V Power Supply
Ground
Memory Organization
No Connection
Program Enable
BLOCK DIAGRAM
VCC
GND
1
CS
2
SK
3
DI
4
DO
ORG
MEMORY ARRAY
ORGANIZATION
ADDRESS
DECODER
Bottom View
DATA
REGISTER
DI
CS
PE*
MODE DECODE
LOGIC
OUTPUT
BUFFER
Note: When the ORG pin is connected to VCC,
the x16 organization is selected. When it is
connected to ground, the x8 pin is selected. If
the ORG pin is left unconnected, then an internal
pullup device will select the x16 organization.
SK
CLOCK
GENERATOR
DO
© 2003 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice.
Doc. No. 1023, Rev. J
93C46/56/57/66/86
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature ........................ -65°C to +150°C
Voltage on any Pin with
Respect to Ground
(1)
............. -2.0V to +V
CC
+2.0V
V
CC
with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Typ
Max
Units
Cycles/Byte
Years
Volts
mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Symbol
I
CC1
I
CC2
I
SB1
I
SB2(5)
I
LI
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current
(Operating Write)
Power Supply Current
(Operating Read)
Power Supply Current
(Standby) (x8 Mode)
Power Supply Current
(Standby) (x16Mode)
Input Leakage Current
Output Leakage Current
(Including ORG pin)
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Test Conditions
f
SK
= 1MHz
V
CC
= 5.0V
f
SK
= 1MHz
V
CC
= 5.0V
CS = 0V
ORG=GND
CS=0V
ORG=Float or V
CC
V
IN
= 0V to V
CC
V
OUT
= 0V to V
CC
,
CS = 0V
4.5V
≤
V
CC
< 5.5V
4.5V
≤
V
CC
< 5.5V
1.8V
≤
V
CC
< 4.5V
4.8V
≤
V
CC
< 4.5V
4.5V
≤
V
CC
< 5.5V
I
OL
= 2.1mA
4.5V
≤
V
CC
< 5.5V
I
OH
= -400µA
1.8V
≤
V
CC
< 4.5V
I
OL
= 1mA
1.8V
≤
V
CC
< 4.5V
I
OH
= -100µA
V
CC
- 0.2
2.4
0.2
-0.1
2
0
V
CC
x 0.7
Min
Typ
Max
3
500
10
0
1
1
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+1
0.4
Units
mA
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) Standby Current (ISB
2
)=0µA (<900nA) for 93C46/56/57/66, (ISB
2
)=2µA for 93C86.
Doc. No. 1023, Rev. J
2
93C46/56/57/66/86
PIN CAPACITANCE
Symbol
C
OUT(3)
C
IN(3)
Test
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Conditions
V
OUT
=0V
V
IN
=0V
Min
Typ
Max
5
5
Units
pF
pF
INSTRUCTION SET
Instruction Device
Type
READ
93C46
93C56
(1)
93C66
93C57
93C86
93C46
93C56
(1)
93C66
93C57
93C86
93C46
93C56
(1)
93C66
93C57
93C86
93C46
93C56
93C66
93C57
93C86
93C46
93C56
93C66
93C57
93C86
93C46
93C56
93C66
93C57
93C86
93C46
93C56
93C66
93C57
93C86
Start Opcode
Bit
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
10
10
10
10
10
11
11
11
11
11
01
01
01
01
01
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Address
x8
x16
A6-A0
A8-A0
A8-A0
A7-A0
A10-A0
A6-A0
A8-A0
A8-A0
A7-A0
A10-A0
A6-A0
A8-A0
A8-A0
A7-A0
A10-A0
11XXXXX
11XXXXXXX
11XXXXXXX
Data
x8
x16
Comments
Read Address AN–A0
PE
(2)
A5-A0
A7-A0
A7-A0
A6-A0
A9-A0
A5-A0
A7-A0
A7-A0
A6-A0
A9-A0
A5-A0
A7-A0
A7-A0
A6-A0
A9-A0
11XXXX
11XXXXXX
11XXXXXX
X
Clear Address AN–A0
ERASE
I
D7-D0
D7-D0
D7-D0
D7-D0
D7-D0
D15-D0
D15-D0
D15-D0
D15-D0
D15-D0
Write Address AN–A0
WRITE
I
Write Enable
EWEN
11XXXXXX
11XXXXX
11XXXXXXXXX 11XXXXXXXX
00XXXXX
00XXXXXXX
00XXXX
00XXXXXX
X
Write Disable
EWDS
00XXXXXXX
00XXXXXX
00XXXXXX
00XXXXX
00XXXXXXXXX 00XXXXXXXX
10XXXXX
10XXXXXXX
10XXXXXXX
10XXXXXX
10XXXX
10XXXXXX
10XXXXXX
10XXXXX
X
Clear All Addresses
ERAL
10XXXXXXXXX 10XXXXXXXX
01XXXXX
01XXXXXXX
01XXXXXXX
01XXXX
01XXXXXX
01XXXXXX
I
D7-D0
D7-D0
D7-D0
D7-D0
D7-D0
D15-D0
D15-D0
D15-D0
D15-D0
D15-D0
Write All Addresses
WRAL
01XXXXXX
01XXXXX
01XXXXXXXXX 01XXXXXXXX
I
Note:
(1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE
and ERASE commands.
(2) Applicable only to 93C86
(3) This parameter is tested initially and after a design or process change that affects the parameter.
3
Doc. No. 1023, Rev. J
93C46/56/57/66/86
A.C. CHARACTERISTICS (93C46/56/57/66)
Limits
V
CC
=
1.8V-6V
Test
SYMBOL PARAMETER
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ(1)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
DC
1
1
1
1
250
DC
C
L
= 100pF
(3)
Conditions
Min
200
0
400
400
1
1
400
10
0.5
0.5
0.5
0.5
500
DC
Max
Min
100
0
200
200
0.5
0.5
200
10
0.25
0.25
0.25
0.25
1000
Max
Min
50
0
100
100
0.25
0.25
100
10
Max
Units
ns
ns
ns
ns
µs
µs
ns
ms
µs
µs
µs
µs
kHz
V
CC
=
2.5V-6V
V
CC
=
4.5V-5.5V
A.C. CHARACTERISTICS (93C86)
Limits
Test
SYMBOL PARAMETER
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ(1)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
DC
1
1
1
1
500
DC
C
L
= 100pF
(3)
Conditions
V
CC
=
1.8V-6V
Min
200
0
200
200
1
1
400
5
0.5
0.5
0.5
0.5
1000
DC
Max
V
CC
=
2.5V-6V
Min
100
0
100
100
0.5
0.5
200
5
0.15
0.15
0.15
0.1
3000
Max
V
CC
=
4.5V-5.5V
Min
50
0
50
50
0.15
0.15
100
5
Max
Units
ns
ns
ns
ns
µs
µs
ns
ms
µs
µs
µs
µs
kHz
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 1023, Rev. J
4
93C46/56/57/66/86
POWER-UP TIMING
(1)(2)
SYMBOL
t
PUR
t
PUW
PARAMETER
Power-up to Read Operation
Power-up to Write Operation
Max
1
1
Units
ms
ms
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
(3) The input levels and timing reference points are shown in “AC Test Conditions” table.
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
≤
50ns
0.4V to 2.4V
0.8V, 2.0V
0.2V
CC
to 0.7V
CC
0.5V
CC
4.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
4.5V
1.8V
≤
V
CC
≤
4.5V
5
Doc. No. 1023, Rev. J
FPGA/CPLD
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