HM6216255H Series
4M high Speed SRAM (256-kword
×
16-bit)
ADE-203-763D (Z)
Rev. 1.0
Sept. 15, 1998
Description
The HM6216255H Series is a 4-Mbit high speed static RAM organized 256-k word
×
16-bit. It has
realized high speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell)
and high speed circuit designing technology. It is most appropriate for the application which requires high
speed, high density memory and wide bit width configuration, such as cache and buffer memory in system.
It is packaged in 400-mil 44-pin plastic SOJ and 400-mil 44-pin plastic TSOPII.
Features
•
Single 5.0 Vsupply : 5.0 V
±
10 %
•
Access time: 10/12/15 ns (max)
•
Completely static memory
No clock or timing strobe required
•
Equal access and cycle times
•
Directly TTL compatible
All inputs and outputs
•
Operating current: 200/180/160 mA (max)
•
TTL standby current: 70/60/50 mA (max)
•
CMOS standby current: 5 mA (max)
: 1.2 mA (max) (L-version)
•
Data retention current: 0.8 mA (max) (L-version)
•
Data retention voltage: 2 V (min) (L-version)
•
Center V
CC
and V
SS
type pinout
HM6216255H Series
Ordering Information
Type No.
HM6216255HJP-10
HM6216255HJP-12
HM6216255HJP-15
HM6216255HLJP-10
HM6216255HLJP-12
HM6216255HLJP-15
HM6216255HTT-10
HM6216255HTT-12
HM6216255HTT-15
HM6216255HLTT-10
HM6216255HLTT-12
HM6216255HLTT-15
Access time
10 ns
12 ns
15 ns
10 ns
12 ns
15 ns
10 ns
12 ns
15 ns
10 ns
12 ns
15 ns
400-mil 44-pin plastic TSOPII (TTP-44DE)
Package
400-mil 44-pin plastic SOJ (CP-44D)
Pin Arrangement
HM6216255HJP/HLJP Series
A0
A1
A2
A3
A4
CS
I/O1
I/O2
I/O3
I/O4
V
CC
V
SS
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
V
SS
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
HM6216255HTT/HLTT Series
A0
A1
A2
A3
A4
CS
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
(Top View)
(Top View)
2
HM6216255H Series
Pin Description
Pin name
A0 to A17
I/O1 to I/O16
CS
OE
WE
Function
Address input
Data input/output
Chip select
Output enable
Write enable
Pin name
UB
LB
V
CC
V
SS
NC
Function
Upper byte select
Lower byte select
Power supply
Ground
No connection
Block Diagram
A1
A17
A7
A11
A16
A2
A6
A5
(MSB)
(LSB)
Row
decoder
Memory matrix
256 rows
×
8 columns
×
128 blocks
×
16 bit
(4,194,304 bits)
Internal
voltage V
CC
generater
V
SS
CS
I/O1
.
.
.
I/O8
I/O9
.
.
.
I/O16
WE
CS
LB
UB
Column I/O
Input
data
control
Column decoder
CS
A10 A8 A9 A12 A13 A14 A0 A15 A3 A4
OE
CS
3
HM6216255H Series
Operation Table
CS
H
L
L
L
L
L
L
L
L
L
Note:
OE
×
H
L
L
L
L
×
×
×
×
WE
×
H
H
H
H
H
L
L
L
L
×:
H or L
LB
×
×
L
L
H
H
L
L
H
H
UB
×
×
L
H
L
H
L
H
L
H
Mode
Standby
Output disable
Read
V
CC
current
I
SB
, I
SB1
I
CC
I
CC
I/O1–I/O8
High-Z
High-Z
Output
Output
High-Z
High-Z
Input
Input
High-Z
High-Z
I/O9–I/O16
High-Z
High-Z
Output
High-Z
Output
High-Z
Input
High-Z
Input
High-Z
Ref. cycle
—
—
Read cycle
Read cycle
Read cycle
—
Write cycle
Write cycle
Write cycle
—
Lower byte read I
CC
Upper byte read I
CC
—
Write
I
CC
I
CC
Lower byte write I
CC
Upper byte write I
CC
—
I
CC
Absolute Maximum Ratings
Parameter
Supply voltage relative to V
SS
Voltage on any pin relative to V
SS
Power dissipation
Operating temperature
Storage temperature
Storage temperature under bias
Notes: 1.
2.
3.
4.
Symbol
V
CC
V
T
P
T
Topr
Tstg
Tbias
Value
–0.5 to +7.0
–0.5*
1
to V
CC
+ 0.5*
2
1.0*
3
/1.3*
4
0 to +70
–55 to +125
–10 to +85
Unit
V
V
W
°C
°C
°C
V
T
(min) = –2.0 V for pulse width (under shoot)
≤
8 ns
V
T
(max) = V
CC
+ 2.0 V for pulse width (over shoot)
≤
8 ns
At still air condition
At air flow
≥
1.0 m/s
4
HM6216255H Series
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter
Supply voltage
Symbol
V
CC
*
2
V
SS
*
3
Input voltage
V
IH
V
IL
Notes: 1.
2.
3.
4.
Min
4.5
0
2.2
–0.5*
1
Typ
5.0
0
—
—
Max
5.5
0
V
CC
+ 0.5*
2
0.8
Unit
V
V
V
V
V
IL
(min) = –2.0 V for pulse width (under shoot)
≤
8 ns
V
IH
(max) = V
CC
+ 2.0 V for pulse width (over shoot)
≤
8 ns
The supply voltage with all V
CC
pins must be on the same level.
The supply voltage with all V
SS
pins must be on the same level.
DC Characteristics
(Ta = 0 to +70°C, V
CC
= 5.0 V
±
10 %, V
SS
= 0 V)
Parameter
Input leakage current
Output leakage
current*
1
Operating power
supply current
10 ns
cycle
12 ns
cycle
15 ns
cycle
Standby power supply 10 ns
current
cycle
12 ns
cycle
15 ns
cycle
Symbol Min
|I
LI
|
|I
LO
|
I
CC
I
CC
I
CC
I
SB
I
SB
I
SB
I
SB1
—
—
—
—
—
—
—
—
—
Typ*
1
—
—
—
—
—
—
—
—
0.1
Max
2
2
200
180
160
70
60
50
5
mA
V
CC
≥
CS
≥
V
CC
– 0.2 V,
(1)
0 V
≤
Vin
≤
0.2 V
or
(2)
V
CC
≥
Vin
≥
V
CC
–
0.2 V
mA
CS
= V
IH
,
Other inputs = V
IH
/V
IL
Unit
µA
µA
mA
Test conditions
Vin = V
SS
to V
CC
Vin = V
SS
to V
CC
CS
= V
IL
, Iout = 0 mA
Other inputs = V
IH
/V
IL
—*
2
Output voltage
V
OL
V
OH
Note:
—
2.4
0.1*
2
—
—
1.2 *
2
0.4
—
V
V
I
OL
= 8 mA
I
OH
= –4 mA
1. Typical values are at V
CC
= 5.0 V, Ta = +25°C and not guaranteed.
2. This characteristics is guaranteed only for L-version.
5
FPGA/CPLD
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