IDT74FCT2541AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS OCTAL
BUFFER/LINE DRIVER
IDT74FCT2541AT/CT
FEATURES:
•
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•
•
•
•
•
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DESCRIPTION:
The IDT octal buffer/line driver is built using an advanced dual metal
CMOS technology. The FCT2541T is similar in function to the FCT2244T,
except that the inputs and outputs are on opposite sides of the package. This
pinout arrangement makes these devices especially useful as output ports
for microprocessors and as backplane drivers, allowing ease of layout and
greater board density.
The FCT2541T has balanced output drive with current limiting resistors.
This offers low ground bounce, minimal undershoot, and controlled output
fall times, reducing the need for external series terminating resistors. The
FCT2541T is a plug-in replacement for the FCT541T.
A and C grades
Low input and output leakage
≤
1µA (max.)
CMOS power levels
True TTL input and output compatibility:
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
Resistor outputs (-15mA I
OH
, 12mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Reduced system switching noise
Available in SOIC, QSOP, and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
OE
A
OE
B
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
NOVEMBER 2003
DSC-5590/3
© 2003 Integrated Device Technology, Inc.
IDT74FCT2541AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE
A
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
OE
B
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
V
TERM
(3)
T
STG
I
OUT
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
C
OUT
SOIC/ QSOP/ TSSOP
TOP VIEW
NOTE:
1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names
OE
A
,
OE
B
Dx
Ox
Inputs
Outputs
Description
3-State Output Enable Inputs (Active LOW)
FUNCTION TABLE
(1)
OE
A
L
L
H
Inputs
OE
B
L
L
H
D
L
H
X
Outputs
L
H
Z
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High Impedance
2
IDT74FCT2541AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±5%
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
I
V
IK
V
H
I
CC
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
High Impedance Output Current
(3-State output pins)
(4)
Input HIGH Current
(4)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max., V
I
= V
CC
(Max.)
V
CC
= Min, I
IN
= -18mA
—
V
CC
= Max., V
IN
= GND or V
CC
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= Max
V
I
= 2.7V
V
I
= 0.5V
V
O
= 2.7V
V
O
= 0.5V
Min.
2
—
—
—
—
—
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
–0.7
200
0.01
Max.
—
0.8
±1
±1
±1
±1
±1
–1.2
—
1
µA
V
mV
mA
Unit
V
V
µA
µA
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
I
ODL
I
ODH
V
OH
V
OL
Parameter
Output LOW Current
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
Test Conditions
(1)
V
CC
= 5V, V
IN
= V
IH
or V
IL
, V
OUT
= 1.5V
(3)
V
CC
= 5V, V
IN
= V
IH
or V
IL
, V
OUT
= 1.5V
(3)
V
CC
= Min
I
OH
= –15mA
V
IN
= V
IH
or V
IL
V
CC
= Min
I
OL
= 12mA
V
IN
= V
IH
or V
IL
Min.
16
–16
2.4
—
Typ.
(2)
48
–48
3.3
0.3
Max.
—
—
—
0.5
Unit
mA
mA
V
V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is ±5µA at T
A
= –55°C.
3
IDT74FCT2541AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
OE
A
=
OE
B
= GND
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
OE
A
=
OE
B
= GND
One Bit Toggling
V
CC
= Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
OE
A
=
OE
B
= GND
Eight Bits Toggling
V
IN
= V
CC
V
IN
= GND
Test Conditions
(1)
Min.
—
—
Typ.
(2)
0.5
0.06
Max.
2
0.12
Unit
mA
mA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
0.6
2.2
mA
—
0.9
3.2
—
1.2
3.4
(5)
—
3.2
11.4
(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input; (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of
∆I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2+ f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Output Frequency
N
i
= Number of Outputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Parameter
Propagation Delay
Dx to Ox
Output Enable Time
Output Disable Time
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
FCT2541AT
Min.
(2)
Max.
1.5
4.8
1.5
1.5
6.2
5.6
FCT2541CT
Min.
(2)
Max.
1.5
4.1
1.5
1.5
5.8
5.2
Unit
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
4
IDT74FCT2541AT/CT
FAST CMOS OCTAL BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V
CC
500Ω
V
IN
Pulse
Generator
R
T
D.U.T
.
V
OUT
7.0V
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
All Other Tests
Switch
Closed
Open
50pF
C
L
500Ω
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
Octal Link
Test Circuits for All Outputs
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t
SU
t
H
t
REM
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
Octal Link
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
1.5V
1.5V
t
SU
t
H
Pulse Width
Octal Link
Set-Up, Hold, and Release Times
ENABLE
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
3V
1.5V
0V
V
OH
1.5V
V
OL
3V
1.5V
0V
CONTROL
INPUT
t
PZL
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
3.5V
1.5V
t
PHZ
DISABLE
3V
1.5V
0V
3.5V
0.3V
0.3V
1.5V
0V
V
OL
V
OH
0V
Octal Link
t
PLZ
Octal Link
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
5
FPGA/CPLD
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