IR3527
DATA SHEET
XPHASE3
TM
DUAL PHASE IC
DESCRIPTION
The IR3527 Dual Phase IC combined with an IR
XPhase3
Control IC provides a full featured and flexible
way to implement multiphase power solutions. The Control IC provides overall system control and interfaces
with any number of IR3527 Phase ICs which each drive and monitor 2 phases of a Synchronous Buck
converter.
The IR3527 implement an independent power savings function for each power stage and sequential phase
timing for use in single output multiphase converters. When power saving mode is enabled, the power stage
will disable its output thus eliminating its switching loss while proper converter operation is maintained by the
single power stage or in conjunction with other converter power stages. The IR3527 current sense amplifiers
remain active when in power savings to support adaptive voltage positioning.
TM
FEATURES
x
x
x
x
x
x
x
x
x
x
x
x
7V/1.3A gate drivers (2.6A GATEL sink current)
Converter output voltage up to 5.1 V (Limited to VCCL-1.4V)
Loss-less inductor current sensing
Feed-forward voltage mode control
Integrated boot-strap synchronous PFET
Self-calibration of PWM ramp, current sense amplifier, and current share amplifier
Single-wire bidirectional average current sharing
Only three external components per phase, plus common decoupling capacitors
Power State Indicator (PSI) interface provides the capability to maximize the efficiency at light loads.
Debugging function isolates phase from the converter
Small thermally enhanced 24L 4 x 4mm MLPQ package
RoHS compliant
VIN (12V)
CCS1
RCS1
CCS2
RCS2
22
25
24
23
CSIN2+
21
20
SW2
GATEH2
CSIN1-
CSIN2-
LGND
VCC
19
1
CSIN1+
EAIN
ISHARE
DACIN
PSI1
PHSOUT
PSI2
PHSIN
GATEH1
BOOST1
BOOST2
VCCL2
18
17
16
15
14
13
CBST2
L2
3 Wire
Analog
Bus
Power
Savings
Control
3 Wire
Digital
Phase
Timing
IC Bias
(7V)
2
3
4
5
6
VOUT+
COUT
IR3527 DUAL
PHASE IC
GATEL2
PGND
GATEL1
VCCL1
VOUT-
CLKIN
L1
SW1
10
11
12
CBST1
7
8
9
CVCCL
CIN
‘
Figure 1 – IR3527 Application Circuit
Page 1 of 20
V3.0
IR3527
ORDERING INFORMATION
Part Number
IR3527MTRPBF
* IR3527MPBF
* Samples only
Package
24 Lead MLPQ
(4 x 4 mm body)
24 Lead MLPQ
(4 x 4 mm body)
Order Quantity
3000 per reel
100 piece strips
PIN DESCRIPTION
PIN#
1
2
3
PIN
SYMBOL
CSIN1+
EAIN
ISHARE
PIN DESCRIPTION
Phase1 current sense amplifier non-inverting input and input to debug comparator
PWM comparator input from the error amplifier output of Control IC. Body Braking
mode is initiated if the voltage on this pin is less than V(DACIN) threshold.
Output of the Current Sense Amplifiers are connected to this pin through 3k
resistors. Voltage on this pin is equal to approximately V(DACIN) + 16 [(V
CSIN1+
–
V
CSIN1-
) + (V
CSIN2+
– V
CSIN2-
)]. Connecting all Phase IC ISHARE pins together creates
a share bus which provides an indication of the average current being supplied by all
the phases. The signal is used by the Control IC for voltage positioning, over-current
protection, and in some cases current reporting. OVP mode is initiated if the voltage
on this pin rises above V(VCCL)- 0.8V.
Reference voltage input from the Control IC. The Current Sense signal and PWM
ramps are referenced to the voltage on this pin.
Input to Phase 1 PSI comparator. Logic low stops the phase from switching (low =
low power state)
Input to Phase 2 PSI comparator. Logic low stops the phase from switching (low =
low power state)
Phase timing clock input.
Phase timing clock output.
Clock input.
Return for Phase1 high-side driver and reference for GATEL1 non-overlap
comparator.
Phase1 High-side driver output and input to GATEL1 non-overlap comparator.
Supply for Phase1 high-side driver. Internal bootstrap synchronous PFET is
connected between this pin and the VCCL1 pin.
Supply for Phase1 low-side driver. Internal bootstrap synchronous PFET is
connected from this pin to the BOOST1 pin.
Phase1 Low-side driver output and input to GATEH1 non-overlap comparator.
Return for low side drivers and reference for GATEH non-overlap comparators.
Phase2 Low-side driver output and input to GATEH2 non-overlap comparator.
Supply for Phase2 low-side driver. Internal bootstrap synchronous PFET is
connected from this pin to the BOOST pin.
Supply for Phase2 high-side driver. Internal bootstrap synchronous PFET is
connected between this pin and the VCCL1 pin.
V3.0
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DACIN
PSI1
PSI2
PHSIN
PHSOUT
CLKIN
SW1
GATEH1
BOOST1
VCCL1
GATEL1
PGND
GATEL2
VCCL2
BOOST2
Page 2 of 20
IR3527
19
20
21
22
23
24
25
GATEH2
SW2
VCC
CSIN2+
CSIN2-
CSIN1-
LGND
Phase2 High-side driver output and input to GATEL2 non-overlap comparator.
Return for Phase2 high-side driver and reference for GATEL2 non-overlap
comparator.
Supply for internal IC circuits. Input to PWM feed-forward.
Phase2 current sense amplifier non-inverting input and input to debug comparator
Phase2 current sense amplifier inverting input
Phase1 current sense amplifier inverting input
Ground for internal IC circuits. IC substrate is connected to this pin.
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated in the operational
sections of the specifications are not implied. All voltages are absolute voltages referenced to the LGND pin.
Operating Junction Temperature…………….. 0 to 150 C
o
o
Storage Temperature Range………………….-65 C to 150 C
MSL Rating………………………………………2
o
Reflow Temperature…………………………….260 C
o
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PIN NAME
CSIN1+
EAIN
ISHARE
DACIN
PSI1
PSI2
PHSIN
PHSOUT
CLKIN
SW1
GATEH1
BOOST1
VCCL1
GATEL1
PGND
GATEL2
VCCL2
BOOST2
V
MAX
8V
8V
8V
3.3V
8V
8V
8V
8V
8V
34V
40V
40V
8V
8V
0.3V
8V
8V
40V
V
MIN
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V DC, -5V for
100ns
-0.3V DC, -5V for
100ns
-0.3V
-0.3V
-0.3V DC, -5V for
100ns
-0.3V
-0.3V DC, -5V for
100ns
-0.3V
-0.3V
I
SOURCE
1mA
1mA
1mA
1mA
1mA
1mA
1mA
2mA
1mA
3A for 100ns,
100mA DC
3A for 100ns,
100mA DC
1A for 100ns,
100mA DC
n/a
5A for 100ns,
200mA DC
5A for 100ns,
200mA DC
5A for 100ns,
200mA DC
n/a
1A for 100ns,
100mA DC
I
SINK
1mA
1mA
1mA
1mA
1mA
1mA
1mA
2mA
1mA
n/a
3A for 100ns,
100mA DC
3A for 100ns,
100mA DC
5A for 100ns,
200mA DC
5A for 100ns,
200mA DC
n/a
5A for 100ns,
200mA DC
5A for 100ns,
200mA DC
3A for 100ns,
100mA DC
V3.0
Page 3 of 20
IR3527
19
20
21
22
23
24
25
GATEH2
SW2
VCC
CSIN2+
CSIN2-
CSIN1-
LGND
40V
34V
34V
8V
8V
8V
n/a
-0.3V DC, -5V for
100ns
-0.3V DC, -5V for
100ns
-0.3V
-0.3V
-0.3V
-0.3V
n/a
3A for 100ns,
100mA DC
3A for 100ns,
100mA DC
n/a
1mA
1mA
1mA
n/a
3A for 100ns,
100mA DC
n/a
20mA
1mA
1mA
1mA
n/a
Note:
1. Maximum GATEHx – SWx = 8V
2.
Maximum BOOSTx – GATEHx = 8V
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH
MARGIN
8.0V
V
CC
28V, 4.75V
VCCL
7.5V, 0 C
T
J
125 C
o
o
ELECTRICAL CHARACTERISTICS
The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions.
Typical values represent the median values, which are related to 25° 0.5V
500kHz
&/.,1
C.
9MHz, 250kHz
3+6,1 0+]
C
GATEH
= 3.3nF, C
GATEL
= 6.8nF (unless otherwise specified).
PARAMETER
Gate Drivers
GATEHx Source
Resistance
GATEHx Sink Resistance
GATELx Source Resistance
GATELx Sink Resistance
GATEHx Source Current
GATEHx Sink Current
GATELx Source Current
GATELx Sink Current
GATEHx Rise Time
GATEHx Fall Time
GATELx Rise Time
GATELx Fall Time
TEST CONDITION
BOOSTx – SWx = 7V. Note 1
BOOSTx – SWx = 7V. Note 1
VCCLx – PGND = 7V. Note 1
VCCLx – PGND = 7V. Note 1
BOOSTx=7V, GATEHx=2.5V, SW=0V.
Note 1
BOOSTx=7V, GATEHx=2.5V, SWx=0V.
Note 1
VCCLx=7V, GATELx=2.5V, PGND=0V.
Note 1
VCCLx=7V, GATELx=2.5V, PGND=0V.
Note 1
BOOSTx – SWx = 7V, measure 1V to 4V
transition time
BOOSTx - SWx = 7V, measure 4V to 1V
transition time
VCCLx – PGND = 7V, Measure 1V to 4V
transition time
VCCLx – PGND = 7V, Measure 4V to 1V
transition time
MIN
TYP
1.3
1.3
1.3
0.5
1.3
1.3
1.3
2.6
6
6
12
6
13
13
26
13
MAX
3.3
3.3
3.3
1.3
UNIT
A
A
A
A
ns
ns
ns
ns
Page 4 of 20
V3.0
IR3527
PARAMETER
GATELx low to GATEHx
high delay
GATEHx low to GATELx
high delay
Disable Pull-Down
Resistance
Clock & Daisy Chain
CLKIN Threshold
CLKIN Bias Current
CLKIN Phase Delay
PHSIN Threshold
PHSOUT Propagation
Delay
PHSIN Pull-Down
Resistance
PHSOUT High Voltage
PHSOUT Low Voltage
PWM Comparators
PWM Ramp Slope
EAIN Bias Current
Minimum Pulse Width
Minimum GATEHx Turn-off
Time
OVP Comparator
OVP Threshold
Propagation Delay
Body Brake Comparator
Threshold Voltage with
EAIN falling.
Threshold Voltage with
EAIN rising.
Hysteresis
Propagation Delay
Measured relative to PWM Ramp Floor
Voltage
Measured relative to PWM Ramp Floor
Voltage
VCCLx = 5V. Measure time from EAIN <
V(DACIN) (200mV overdrive) to GATELx
transition to < 4V.
-340
-240
70
40
-235
-135
105
65
-130
-30
130
90
mV
mV
mV
ns
Vin=12V
0
EAIN
3V
Note 1
20
Step V(ISHARE) up until GATELx drives
high. Compare to V(VCCLx)
V(VCCLx)=5V, Step V(ISHARE) up from
V(DACIN) to V(VCCLx). Measure time to
V(GATELx)>4V.
-1.0
15
42
-5
52.5
-0.3
65
80
-0.8
40
57
5
75
160
-0.4
70
mV/
%DC
PA
ns
ns
V
ns
TEST CONDITION
BOOSTx = VCCLx = 7V, SWx = PGND = 0V,
measure time from GATELx falling to 1V to
GATEHx rising to 1V
BOOSTx = VCCLx = 7V, SWx = PGND =
0V, measure time from GATEHx falling to 1V
to GATELx rising to 1V
Note 1
MIN
10
10
30
TYP
20
20
80
MAX
40
40
130
UNIT
ns
ns
N
Compare to V(VCCLx)
CLKIN = V(VCCLx)
Measure time from CLKIN<1V to
GATEHx>1V
Compare to V(VCCLx)
Measure time from CLKIN > (VCCLx*50%)
o
to PHSOUT>(VCCLx*50%). 10pF@125 C
40
-0.5
40
35
4
30
45
0.0
75
50
15
100
0.6
0.4
57
0.5
125
55
35
170
PA
ns
%
ns
N
V
%
I(PHSOUT) = -5mA, measure VCCLx –
PHSOUT
I(PHSOUT) = 5mA
2
2
V
Page 5 of 20
V3.0
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