HY62UF16201A/ HY62QF16201A/ HY62EF16201A/
HY62SF16201A Series
128Kx16bit full CMOS SRAM
PRELIMINARY
DESCRIPTION
The HY62UF16201A / HY62QF16201A /
HY62EF16201A / HY62SF16201A is a high
speed, super low power and 2Mbit full CMOS
SRAM organized as 131,072 words by 16bits. The
HY62UF16201A
/
HY62QF16201A
/
HY62EF16201A / HY62SF16201A uses high
performance full CMOS process technology and
is designed for high speed and low power circuit
technology. It is particularly well-suited for the
high density low power system application. This
device has a data retention mode that guarantees
data to remain valid at a minimum power supply
voltage of 1.5V.
FEATURES
•
Fully static operation and Tri-state output
•
TTL compatible inputs and outputs
•
Battery backup(LL/SL-part)
- 1.5V(min) data retention
•
Standard pin configuration
- 48ball CSP
Product
Voltage
Speed
Operation
Standby Current(uA)
No.
(V)
(ns)
Current(mA)
LL
SL
HY62UF16201A
3.0
55/70/85
15
10
2
HY62UF16201A-I
3.0
55/70/85
15
10
2
HY62QF16201A
2.5
70/85/100
10
10
2
HY62QF16201A-I
2.5
70/85/100
10
10
2
HY62EF16201A
2.0
85/100/120
10
10
2
HY62EF16201A-I
2.0
85/100/120
10
10
2
HY62SF16201A
1.8
100/120/150
10
10
2
HY62SF16201A-I
1.8
100/120/150
10
10
2
Note 1. E.T. : Extended Temperature, Normal : Normal Temperature
2. Current value is max.
Temperature
(°C)
0~70(Normal)
-40~85(E.T.)
0~70(Normal)
-40~85(E.T.)
0~70(Normal)
-40~85(E.T.)
0~70(Normal)
-40~85(E.T.)
PIN CONNECTION
(Top View )
ADD INPUT
BUFFER
A1,A2
A4, A6~A7
A9
BLOCK DIAGRAM
SENSE AMP
ROW
DECODER
I/O1
PRE-DECODER
IO9 /UB A3
IO10 IO11 A5
Vss IO12 NC
Vcc IO13 NC
A4
A6
A7
/CS IO1
IO2 IO3
IO4 Vcc
A13
A14
A0
A3
A5
A11
/CS
/OE
/LB
/UB
/WE
ADD INPUT
BUFFER
BLOCK
DECODER
MEMORY ARRAY
512x128x32
WRITE DRIVER
A10
ADD INPUT
BUFFER
OUTPUT
BUFFER
A15~A16
A8
COLUMN
DECODER
/LB
/OE A0
A1
A2
NC
A12
I/O8
I/O9
A16 IO5 Vss
I/O16
IO15 IO14 A14 A15 IO6 IO7
IO16 NC
NC
A8
A12 A13 /WE IO8
A9
A10 A11 NC
PIN DESCRIPTION
Pin Name
/CS
/WE
/OE
/LB
/UB
Pin Funtion
Chip Select
Write Enable
Output Enable
Lower Byte Control(I/O1~I/O8)
Upper Byte Control(I/O9~I/O16)
Pin Name
I/O1~I/O16
A0~A16
Vcc
Vss
NC
Pin Funtion
Data Input/Output
Address Input
Power(3.0V/2.5V/2.0V/1.8V)
Ground
No Connection
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.01 /Feb. 99
Hyundai Semiconductor
HY62UF16201A/HY62QF16201A/HY62EF16201A/HY62SF16201A Series
ORDERING INFORMATION
Part No.
HY62UF16201ALLM
HY62UF16201ASLM
HY62UF16201ALLM-I
HY62UF16201ASLM-I
HY62QF16201ALLM
HY62QF16201ASLM
HY62QF16201ALLM-I
HY62QF16201ASLM-I
HY62EF16201ALLM
HY62EF16201ASLM
HY62EF16201ALLM-I
HY62EF16201ASLM-I
HY62SF16201ALLM
HY62SF16201ASLM
HY62SF16201ALLM-I
HY62SF16201ASLM-I
Speed
55/70/85
55/70/85
55/70/85
55/70/85
70/85/100
70/85/100
70/85/100
70/85/100
85/100/120
85/100/120
85/100/120
85/100/120
100/120/150
100/120/150
100/120/150
100/120/150
Power
LL-part
SL-part
LL-part
SL-part
LL-part
SL-part
LL-part
SL-part
LL-part
SL-part
LL-part
SL-part
LL-part
SL-part
LL-part
SL-part
Temp.
Package
CSP
CSP
CSP
CSP
CSP
CSP
CSP
CSP
CSP
CSP
CSP
CSP
CSP
CSP
CSP
CSP
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
Note 1. E.T. : Extended Temperature, Blank : Normal Temperature
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
V
IN,
V
OUT
Vcc
T
A
Parameter
Input/Output Voltage
Power Supply
Operating Temperature
Rating
-0.2 to 3.6
-0.2 to 4.6
0 to 70
Unit
V
V
°C
Remark
-40 to 85
°C
HY62UF16201A
HY62QF16201A
HY62EF16201A
HY62SF16201A
HY62UF16201A-I
HY62QF16201A-I
HY62EF16201A-I
HY62SF16201A-I
T
STG
P
D
T
SOLDER
Storage Temperature
Power Dissipation
Ball Soldering Temperature & Time
-55 to 150
1.0
260
•
10
°C
W
°C•sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
Rev.01 / Feb. 99
2
HY62UF16201A/HY62QF16201A/HY62EF16201A/HY62SF16201A Series
RECOMMENDED DC OPERATING CONDITION
Symbol
Vcc
Parameter
Supply Voltage
Product
HY62UF16201A-(I)
HY62QF16201A-(I)
HY62EF16201A-(I)
HY62SF16201A-(I)
HY62UF16201A-(I)
HY62QF16201A-(I)
HY62EF16201A-(I)
HY62SF16201A-(I)
HY62UF16201A-(I)
HY62QF16201A-(I)
HY62EF16201A-(I)
HY62SF16201A-(I)
HY62UF16201A-(I)
HY62QF16201A-(I)
HY62EF16201A-(I)
HY62SF16201A-(I)
Min.
2.7
2.2
1.8
1.6
0
Typ.
3.0
2.5
2.0
1.8
0
Max.
3.6
2.8
2.2
2.0
0
Unit
V
V
V
V
Vss
Ground
V
IH
Input High Voltage
V
IL
Input Low Voltage
2.2
2.0
1.6
1.4
-0.3
(1)
-
-
-
-
Vcc+0.3
Vcc+0.3
Vcc+0.3
Vcc+0.3
0.4
V
V
V
V
V
Note : 1. VIL = -1.5V for pulse width less than 30ns
TRUTH TABLE
/CS
H
L
L
L
/WE
X
H
X
H
/OE
X
H
X
L
/LB
X
X
H
L
H
L
L
H
L
/UB
X
X
H
H
L
L
H
L
L
Mode
Not Selected
Output Disabled
Not Selected
Read
I/O Pin
I/O1~I/O8
I/O9~I/O16
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
D
OUT
Hi-Z
Hi-Z
D
OUT
D
OUT
D
OUT
D
IN
Hi-Z
Hi-Z
D
IN
D
IN
D
IN
Supply Current
I
SB
, I
SB1
Icc
I
SB
, I
SB1
Icc
1
L
L
X
Write
Icc
1
Note:
1. H=V
IH
, L=V
IL
, X=don't care
2. UB, LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When LB is LOW, data is written or read to the lower byte, I/O 1 -I/O 8.
When UB is LOW, data is written or read to the upper byte, I/O 9 -I/O 16.
Rev.01 / Feb. 99
3
HY62UF16201A/HY62QF16201A/HY62EF16201A/HY62SF16201A Series
DC ELECTRICAL CHARACTERISTICS
Vcc = 2.7V~3.6V/2.5V±10%/2.0V±10%/1.8V±10%, T
A
= 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.)
Sym
Parameter
Test Condition
Min Typ Max
I
LI
Input Leakage Current
Vss < V
IN
< Vcc
-1
-
1
I
LO
Output Leakage Current
Vss < V
OUT
< Vcc, /CS = V
IH
or
-1
-
1
/
OE
=
V
IH
or /WE = V
IL
/
UB
=
V
IH
or /LB = V
IH
Icc
Operating HY62UF16201A-(I) /CS = V
IL
,
Vcc = 3.0V
-
8
15
Power
HY62QF16201A-(I) V
IN
= V
IH
or V
IL
Vcc = 2.5V/2V/
-
5
10
Supply
HY62EF16201A-(I) I
I/O =
0mA
1.8V
Current
HY62SF16201A-(I)
I
CC1
Average
HY62UF16201A-(I) /CS = V
IL,
Min Duty Cycle = 100%
-
-
80
Operating HY62QF16201A-(I) I
I/O =
0mA
-
-
60
Current
HY62EF16201A-(I)
-
-
40
HY62SF16201A-(I)
-
-
35
I
SB
TTL
HY62UF16201A-(I) /CS = V
IH
or /CS = V
IL,
-
-
1
Standby
HY62QF16201A-(I) /UB, /LB = V
IH
-
-
0.5
Current
HY62EF16201A-(I)
-
-
0.5
(TTL Input)
HY62SF16201A-(I)
-
-
0.5
I
SB1
Standby Current
/CS > Vcc - 0.2V or /CS < Vss
SL
-
-
2
(CMOS Input)
+ 0.2V, /UB, /LB > Vcc - 0.2V
LL
-
-
10
V
OL
Output
HY62UF16201A-(I) Vcc = 3.0V
I
OL
= 2.1mA
-
-
0.4
Low
HY62QF16201A-(I) Vcc = 2.5V
I
OL
= 0.5mA
Voltage
HY62EF16201A-(I) Vcc = 2.0V
I
OL
= 0.33mA
HY62SF16201A-(I) Vcc = 1.8V
I
OL
= 0.26mA
V
OH
Output
HY62UF16201A-(I) Vcc = 3.0V
I
OH =
-1.0mA
2.2
-
-
High
HY62QF16201A-(I) Vcc = 2.5V
I
OH =
-0.5mA
2.0
-
-
Voltage
HY62EF16201A-(I) Vcc = 2.0V
I
OH =
-0.44mA
1.6
-
-
HY62SF16201A-(I) Vcc = 1.8V
I
OH =
-0.44mA
1.4
-
-
Note : Typical values are at Vcc = 3.0V/2.5V/2.0V/1.8V, T
A
= 25°C
Unit
uA
uA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
uA
V
V
V
V
V
Rev.01 / Feb. 99
4
HY62UF16201A/HY62QF16201A/HY62EF16201A/HY62SF16201A Series
AC CHARACTERISTICS
Vcc = 2.7V~3.6V, T
A
= 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified
-55
-70
-85
# Symbol
Parameter
Min.
Max. Min.
Max. Min
Max.
READ CYCLE
1
tRC
Read Cycle Time
55
-
70
-
85
-
2
tAA
Address Access Time
-
55
-
70
-
85
3
tACS
Chip Select Access Time
-
55
-
70
-
85
4
tOE
Output Enable to Output Valid
-
35
-
40
-
45
5
tBA
/LB, /UB Access Time
-
55
-
70
-
85
6
tCLZ
Chip Select to Output in Low Z
10
-
10
-
10
-
7
tOLZ
Output Enable to Output in Low Z
5
-
5
-
5
-
8
tBLZ
/LB, /UB Enable to Output in Low Z
5
-
5
-
5
-
9
tCHZ
Chip Deselection to Output in High Z
0
30
0
30
0
30
10 tOHZ
Out Disable to Output in High Z
0
30
0
30
0
30
11 tBHZ
/LB, /UB Disable to Output in High Z
0
30
0
30
0
30
12 tOH
Output Hold from Address Change
10
-
10
-
10
-
WRITE CYCLE
13 tWC
Write Cycle Time
55
-
70
-
85
-
14 tCW
Chip Selection to End of Write
50
-
60
-
70
-
15 tAW
Address Valid to End of Write
50
-
60
-
70
-
16 tBW
/LB, /UB Valid to End of Write
50
-
60
-
70
-
17 tAS
Address Set-up Time
0
-
0
-
0
-
18 tWP
Write Pulse Width
45
-
50
-
55
-
19 tWR
Write Recovery Time
0
-
0
-
0
-
20 tWHZ
Write to Output in High Z
0
20
0
25
0
30
21 tDW
Data to Write Time Overlap
25
-
30
-
35
-
22 tDH
Data Hold from Write Time
0
-
0
-
0
-
23 tOW
Output Active from End of Write
5
-
5
-
5
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev.01 / Feb. 99
5
FPGA/CPLD
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