CMX980A
TETRA
Baseband Processor
D/980A/3
October 1999
Advance Information
1.0
Features
•
RRC Filters for both Tx and Rx
•
•
4 x 10-Bit D-A and 4 Input 10-Bit A-D
•
Transmit Output Power Control
•
Low Power 3.0 - 5.5Volt Operation
•
Effective Power down Modes
π
/4 DQPSK Modulation
•
2 x 14-Bit Resolution Sigma Delta D-A
•
2 x 16-Bit Resolution Sigma Delta A-D
1.1
Brief Description
This device is intended to act as an interface between the analogue and digital sections of a Digital Radio
System, and performs many critical and DSP-intensive functions. The chip is designed with the necessary
capability to meet the requirements for use in both mobile and base station applications in Terrestrial Trunked
Radio (TETRA) systems, but the architecture is sufficiently flexible to allow use in other systems.
The transmit path comprises all the circuitry required to convert digital data into suitably filtered analogue
I and Q signals for subsequent up-conversion and transmission. This includes digital control of the output
amplitudes, digital control of the output offsets and fully programmable digital filters: default coefficients
provide the RRC response required for TETRA.
The receive section accepts differential analogue I and Q signals at baseband and converts these into a
suitably filtered digital form for further processing and data extraction. A facility is provided for digital offset
correction and the digital filters are fully programmable with default coefficients providing the RRC response
required for TETRA.
Auxiliary DAC and ADC functions are included for the control and measurement of the RF section of the radio
system. This may include AFC, AGC, RSSI, or may be used as part of the control system for a Cartesian
Loop.
©
1999
Consumer Microcircuits Limited
TETRA Baseband Processor
CMX980A
CONTENTS
Section
Page
1.0 FEATURES ....................................................................................................................................... 1
1.1 BRIEF DESCRIPTION....................................................................................................................... 1
1.2 BLOCK DIAGRAM ............................................................................................................................ 5
1.3 SIGNAL LIST .................................................................................................................................... 6
1.4 EXTERNAL COMPONENTS ............................................................................................................. 8
1.5 GENERAL DESCRIPTION ................................................................................................................ 9
1.5.1 Connection and Decoupling of Power Supplies...................................................................
9
1.5.2 Programmable FIR filter Architecture
.................................................................................. 10
1.5.3 Tx Data Path
.......................................................................................................................... 11
1.5.3.1 Modulator............................................................................................................................ 11
1.5.3.2 Filters.................................................................................................................................. 11
1.5.3.3 Gain Multiplier ...................................................................................................................... 11
1.5.3.4 Offset Adjust ........................................................................................................................ 11
1.5.3.5 Sigma-Delta D-A Converters and Reconstruction Filters....................................................... 11
1.5.3.6 Phase Pre-distortion............................................................................................................. 11
1.5.3.7 Ramping Output Amplitude .................................................................................................. 11
1.5.3.8 Symbol Clock Phase Adjustment.......................................................................................... 12
1.5.3.9 Direct Write to Tx 79-tap Filter Input..................................................................................... 12
1.5.3.10 Test Access to DAC Input .................................................................................................. 12
1.5.4 Rx Data Path..........................................................................................................................
13
1.5.4.1 Anti-Alias Filtering and Sigma-Delta A-D Converters ............................................................ 13
1.5.4.2 Rx FIR Filters....................................................................................................................... 13
1.5.4.3 Offset Registers ................................................................................................................... 13
1.5.4.4 I and Q Channel Gain........................................................................................................... 13
1.5.5 Auxiliary Circuits
.................................................................................................................. 14
1.5.5.1 10-Bit DACs ......................................................................................................................... 14
1.5.5.2 10-Bit ADC........................................................................................................................... 14
1.5.5.3 Power Ramping and Control................................................................................................. 14
1.5.6 IRQ Function
......................................................................................................................... 14
1.5.7 Serial Interface
...................................................................................................................... 15
1.5.7.1 Command Interface.............................................................................................................. 16
1.5.7.2 Command Read Interface .................................................................................................... 16
1.5.7.3 Rx Data Interface ................................................................................................................. 16
1.5.7.4 Transmission of Data ........................................................................................................... 16
1.5.7.5 Command Control Serial Word............................................................................................. 18
1.5.7.6 Coefficient Memory .............................................................................................................. 20
1.5.7.7 Auto Power Save Mode........................................................................................................ 20
1.5.8 Register Description
............................................................................................................. 21
1.5.8.1 Register and Access Point Summary ................................................................................... 22
1.6 APPLICATION NOTES ................................................................................................................... 85
1.6.1 Interrupt Handling.................................................................................................................
85
1.6.2 Configuration
........................................................................................................................ 85
1.6.3 Reset......................................................................................................................................
85
1.6.4 Developing and Optimising FIR Filter Coefficients
............................................................ 85
©
1999
Consumer Microcircuits Limited
2
D/980A/3
TETRA Baseband Processor
CMX980A
1.6.4.1 Tx Path Details..................................................................................................................... 86
1.6.4.2 Rx Path Details .................................................................................................................... 87
1.6.4.3 General Procedure for Reconfiguring the CMX980A Filters .................................................. 88
1.6.5 Generating a Transmit Frame Sequence with optimal use of ramping features...............
88
1.6.6 Internal Symbol-Clock Phase Adjustment...........................................................................
88
1.6.7 Receiver Re-Synchronisation...............................................................................................
89
1.6.8 Guidelines for use of Power Save Modes
........................................................................... 90
1.6.8.1 Auxiliary Section................................................................................................................... 90
1.6.8.2 Tx Section............................................................................................................................ 90
1.6.8.3 Rx Section ........................................................................................................................... 90
1.6.8.4 Tx and Rx Bias Section ........................................................................................................ 90
1.6.8.5 Serial Interface Section ........................................................................................................ 91
1.7 PERFORMANCE SPECIFICATION................................................................................................. 92
1.7.1 Electrical Performance
......................................................................................................... 92
1.7.1.1 Absolute Maximum Ratings.................................................................................................. 92
1.7.1.2 Operating Limits................................................................................................................... 92
1.7.1.3 Operating Characteristics ..................................................................................................... 93
1.7.2 Packaging............................................................................................................................
106
Note:
This product is in development: Changes and additions will be made to this
specification. Items marked TBD or left blank will be included in later issues.
Information in this data sheet should not be relied upon for final product design.
©
1999
Consumer Microcircuits Limited
3
D/980A/3
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