The MBM29XL12DF is 128M-bit, 3.0 V-only Page mode and dual operation Flash memory organized as 8M
words by 16 bits or 4M words by 32 bits. The device is offered in 90-pin SSOP and 96-ball FBGA packages.
This device is designed to be programmed in-system with the standard system 3.0 V Vcc supply. 12.0 V Vpp
and 5.0 V Vcc are not required for program or erase operations. The device can also be reprogrammed in
standard EPROM programmers.
The device provides truly high performance non-volatile Flash memory solution. The device offers fast page
access times of 25ns and 30ns with random access times of 70ns and 75ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE),
(Continued)
write enable (WE), and output enable (OE) controls. The page size is 8 words or 4 double words.
s
PRODUCT LINEUP
Part No.
Ordering Part Number Suffix
V
CC
(V)
V
CCQ
(V)
Max. Random Address Access Time (ns)
Max. Page Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
70
3.0 to 3.6
V
CC
70
25
70
25
MBM29XL12DF
80
2.7 to 3.1
V
CC
75
30
75
30
s
PACKAGES
90-pin plastic SSOP
96-ball plastic FBGA
(FPT-90P-M01)
(BGA-96P-M02)
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
This document contains information on product under development at Fujitsu. The information is intended to help you evaluate this product. Fujitsu reserves the
right to change this proposed product without notice.
MBM29XL12DF
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(Continued)
The dual operation function provides simultaneous operation by dividing the memory space into four banks. The
device can improve overall system performance by allowing a host system to program or erase in one bank,
then immediately and simultaneously read from the other bank with zero latency. This releases the system from
waiting for the completion of program or erase operations.
The device is command set compatible with JEDEC standard E
2
PROMs. Commands are written to the command
register using standard microprocessor write timings. Register contents serve as input to an internal state-
machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and
data needed for the program and erase operations. Reading data out of the device is similar to reading from 5.0
V and 12.0 V Flash or EPROM devices.
The device is programmed by executing the program command sequence. This will invoke the Embedded
Program Algorithm
TM
which is an internal algorithm that automatically times the program pulse widths and verifies
proper cell margins. Typically, each 32K words sector can be programmed and verified in about 0.3 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm
TM
which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margins.
Any individual sector is typically erased and verified in 0.5 seconds. (If already preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The device is erased when shipped from the factory.
The Enhanced V
I/O
(V
CCQ
) feature allows the output voltage generated on the device to be determined based on
the V
I/O
level. This feature allows this device to operate in the 1.8 V I/O environment, driving and receiving signals
to and from other 1.8 V devices on the same bus.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits program and erase operations on the loss of power. The end of program or erase is detected by Data
Polling of DQ
7
, by the Toggle Bit feature on DQ
6
, output pin. Once the end of a program or erase cycle has been
completed, the device internally resets to the read mode.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The device memory electrically erases all bits within a sector
simultaneously via Fowler-Nordhiem tunneling. The words are programmed one word at a time using the EPROM
programming mechanism of hot electron injection.
2 (AE1.0E) Preliminary
MBM29XL12DF
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s
FEATURES
• 0.17
µ
m Process Technology
• Single 3.0 V Read, Program and Erase
Minimized system level power requirements
• Simultaneous Read/Write (Program and Erase) Operations (Dual Bank)
• FlexBank
TM
Bank A: 16 Mbit (4K words
×8
and 32K words
×31)
Bank B: 48 Mbit (32K words
×96)
Bank C: 48 Mbit (32K words
×96)
Bank D: 16 Mbit (4K words
×8
and 32K words
×31)
• Enhanced V
I/O
(V
CCQ
) Feature
Input/Output voltage generated on the device is determined based on the V
I/O
level
• High Performance Page Mode
25ns maximum page access time at V
CC
= 3.0 to 3.6V and V
CCQ
= V
CC
(70ns random access time)
30ns maximum page access time at V
CC
= 2.7 to 3.1V and V
CCQ
= V
CC
(75ns random access time)
• 8 Words Page (×16) / 4 Double Words Page (×32) Size
×
×
• Compatible with JEDEC-Standard Commands
Uses same software commands as E
2
PROMs
• Compatible with JEDEC-standard World-wide Pinouts
90-pin SSOP (Package Suffix : PFV)
96-ball FBGA (Package Suffix : PBT)
• Minimum 100,000 Program/Erase Cycles
• Sector Erase Architecture
Eight 4K words, two hundred fifty -four 32K words, and eight 4K words sectors
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Dual Boot Block
16 by 4K words bootblock sectors, 8 at the top of the address range and 8 at the bottom of the address range
• HiddenROM
TM
Region
128 words of HiddenROM region by using device address of word mode 000000h to 00007Fh (double word
mode: 000000h to 00003Fh) accessible through a “HiddenROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• Write Protect Pin (WP)
Write Protect (WP) function allows protection of “outermost” 2× 4K words on both ends of boot sectors,
regardless of sector protection/unprotection status
• Accelerate Pin (ACC)
At V
ACC
, increases program performance
• Embedded Erase
TM
Algorithms
Automatically preprograms and erases the chip or any sector
• Embedded Program
TM
Algorithms
Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit Feature for detection of program or erase cycle completion
• Ready/Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
When addresses remain stable, the device automatically switches itself to low power mode.
• Low V
CC
Write Inhibit
≤
V
LKO
• Program Suspend/Resume
Suspends the program operation to allow a read in another word
Preliminary (AE1.0E) 3
MBM29XL12DF
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(Continued)
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• In accordance with CFI (Common Flash Memory Interface)
• Hardware Reset Pin (RESET)
Hardware method to reset the device for reading array data
• New Sector Protection
Persistent Sector Protection
Password Sector Protection
• Hardware Sector Group Protection
Hardware method disables any combination of sectors from program or erase operation
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