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MTB30P06V
Preferred Device
Power MOSFET
30 Amps, 60 Volts
P−Channel D
2
PAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage
transients.
Features
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30 AMPERES, 60 VOLTS
R
DS(on)
= 80 mW
P−Channel
D
•
Avalanche Energy Specified
•
I
DSS
and V
DS(on)
Specified at Elevated Temperature
•
Pb−Free Packages are Available
MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (R
GS
= 1.0 MW)
Gate−to−Source Voltage
− Continuous
− Non−repetitive (t
p
≤
10 ms)
Drain Current − Continuous @ 25°C
− Continuous @ 100°C
− Single Pulse (t
p
≤
10
ms)
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ T
A
= 25°C
(Note 1)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
J
= 25°C
(V
DD
= 25 Vdc, V
GS
= 10 Vdc, Peak
I
L
= 30 Apk, L = 1.0 mH, R
G
= 25
W)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
− Junction−to−Ambient (Note 1)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 seconds
Symbol
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
D
I
DM
P
D
Value
60
60
±
15
±
25
30
19
105
125
0.83
3.0
−55 to
175
450
Unit
Vdc
Vdc
1
G
S
D
2
PAK
CASE 418B
STYLE 2
MARKING DIAGRAM & PIN ASSIGNMENT
Vdc
Vpk
Adc
Apk
W
W/°C
1
Gate
A
Y
WW
G
4 Drain
MTB
30P06VG
AYWW
3
2
Source
Drain
T
J
, T
stg
E
AS
°C
mJ
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
°C/W
R
qJC
R
qJA
R
qJA
T
L
1.2
62.5
50
260
°C
Device
MTB30P06V
MTB30P06VG
MTB30P06VT4
MTB30P06VT4G
Package
D
2
PAK
D
2
PAK
(Pb−Free)
D
2
PAK
D
2
PAK
(Pb−Free)
Shipping
†
50 Units/Rail
50 Units/Rail
800/Tape & Reel
800/Tape & Reel
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2006
1
July, 2006 − Rev.4
Publication Order Number:
MTB30P06V/D
MTB30P06V
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 0.25 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 60 Vdc, V
GS
= 0 Vdc)
(V
DS
= 60 Vdc, V
GS
= 0 Vdc, T
J
= 150°C)
Gate−Body Leakage Current (V
GS
=
±
15 Vdc, V
DS
= 0 Vdc)
ON CHARACTERISTICS
(Note 2)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
mAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−Source On−Resistance (V
GS
= 10 Vdc, I
D
= 15 Adc)
Drain−Source On−Voltage
(V
GS
= 10 Vdc, I
D
= 30 Adc)
(V
GS
= 10 Vdc, I
D
= 15 Adc, T
J
= 150°C)
Forward Transconductance
(V
DS
= 8.3 Vdc, I
D
= 15 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 3)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(V
DS
= 48 Vdc, I
D
= 30 Adc,
V
GS
= 10 Vdc)
(V
DD
= 30 Vdc, I
D
= 30 Adc,
V
GS
= 10 Vdc, R
G
= 9.1
W)
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I
S
= 30 Adc, V
GS
= 0 Vdc)
(I
S
= 30 Adc, V
GS
= 0 Vdc, T
J
= 150°C)
V
SD
−
−
t
rr
(I
S
= 30 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/ms)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
2. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2%.
3. Switching characteristics are independent of operating junction temperature.
L
D
−
L
S
−
3.5
4.5
7.5
−
−
nH
nH
t
a
t
b
Q
RR
−
−
−
−
2.3
1.9
175
107
68
0.965
3.0
−
−
−
−
−
mC
ns
Vdc
−
−
−
−
−
−
−
−
14.7
25.9
98
52.4
54
9.0
26
20
30
50
200
100
80
−
−
−
nC
ns
(V
DS
= 25 Vdc, V
GS
= 0 Vdc, f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
1562
524
154
2190
730
310
pF
V
GS(th)
2.0
−
R
DS(on)
V
DS(on)
−
−
g
FS
5.0
7.9
−
2.0
−
2.9
2.8
Mhos
−
2.6
5.3
0.067
4.0
−
0.08
Vdc
mV/°C
W
Vdc
V
(BR)DSS
60
−
I
DSS
−
−
I
GSS
−
−
−
−
10
100
100
nAdc
−
62
−
−
Vdc
mV/°C
mAdc
Symbol
Min
Typ
Max
Unit
Reverse Recovery Time
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2
MTB30P06V
TYPICAL ELECTRICAL CHARACTERISTICS
60
T
J
= 25°C
I D , DRAIN CURRENT (AMPS)
50
40
30
20
10
0
5V
4V
0
2
4
6
8
10
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
12
6V
V
GS
= 10V
9V
8V
7V
I D , DRAIN CURRENT (AMPS)
50
40
30
20
10
0
T
J
= −55°C
60
V
DS
≥
10 V
100°C
25°C
0
1
2
3
4
5
6
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
7
8
Figure 1. On−Region Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.12
V
GS
= 10 V
0.1
0.08
0.06
− 55°C
0.04
0.02
0
T
J
= 100°C
0.08
T
J
= 25°C
0.07
V
GS
= 10 V
25°C
15 V
0.06
0.05
0
10
20
30
40
I
D
, DRAIN CURRENT (AMPS)
50
60
0.04
0
10
20
30
40
I
D
, DRAIN CURRENT (AMPS)
50
60
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
R DS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
−50
−25
0
25
50
75
100 125
T
J
, JUNCTION TEMPERATURE (°C)
150
175
V
GS
= 10 V
I
D
= 15 A
I DSS , LEAKAGE (nA)
100
V
GS
= 0 V
T
J
= 125°C
10
100°C
1
0
50
60
10
20
30
40
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
70
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
MTB30P06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
− V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
− V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
6000
5000
C, CAPACITANCE (pF)
4000
3000
2000
1000
0
10
C
iss
V
DS
= 0 V
V
GS
= 0 V
T
J
= 25°C
C
rss
C
iss
C
oss
C
rss
5
V
GS
0
V
DS
5
10
15
20
25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
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