ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8305I is a low skew, 1-to-4, Differential/LVCMOS-to-
LVCMOS/LVTTL Fanout Buffer. The ICS8305I has selectable
clock inputs that accept either differential or single ended
input levels. The clock enable is internally synchronized to
eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin. Outputs are
forced LOW when the clock is disabled. A separate output
enable pin controls whether the outputs are in the active or
high impedance state.
Guaranteed output and part-to-part skew characteristics make
the ICS8305I ideal for those applications demanding well de-
fined performance and repeatability.
F
EATURES
• 4 LVCMOS/LVTTL outputs
• Selectable differential or LVCMOS/LVTTL clock inputs
•
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• LVCMOS_CLK supports the following input types:
LVCMOS, LVTTL
• Maximum output frequency: 350MHz
• Output skew: 40ps (maximum)
• Part-to-part skew: 700ps (maximum)
•
Additive phase jitter, RMS: 0.04ps (typical)
• 3.3V core, 3.3V, 2.5V or 1.8V output operating supply
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
B
LOCK
D
IAGRAM
CLK_EN
D
Q
LE
LVCMOS_CLK
CLK
nCLK
CLK_SEL
Q2
P
IN
A
SSIGNMENT
GND
OE
V
DD
CLK_EN
CLK
nCLK
CLK_SEL
LVCMOS_CLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q0
V
DDO
Q1
GND
Q2
V
DDO
Q3
GND
0
0
1
1
Q0
Q1
ICS8305I
16-Lead TSSOP
4.4mm x 3.0mm x 0.92mm package body
G Package
Top View
Q3
OE
8305AGI
www.idt.com
1
REV. B JULY 29, 2010
ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 9, 13
2
3
4
5
6
7
8
10, 12, 14, 16
11, 15
Name
GND
OE
V
DD
CLK_EN
CLK
nCLK
CLK_SEL
LVCMOS_CLK
Q3, Q2, Q1, Q0
V
DDO
Power
Input
Power
Input
Input
Input
Input
Input
Output
Power
Type
Description
Power supply ground.
Output enable. When LOW, outputs are in HIGH impedance state.
Pullup
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
Core supply pin.
Synchronizing clock enable. When LOW, the output clocks are
disabled. When HIGH, output clocks are enabled.
Pullup
LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Pullup/
Inver ting differential clock input. V
DD
/2 default when left floating.
Pulldown
Clock select input. When HIGH, selects CLK, nCLK inputs.
Pullup
When LOW, selects LVCMOS_CLK input.
LVCMOS / LVTTL interface levels.
Pulldown LVCMOS / LVTTL clock input.
Clock outputs. LVCMOS / LVTTL interface levels.
Output supply pins.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
Minimum
Typical
4
51
51
11
5
7
12
Maximum
Units
pF
kΩ
kΩ
pF
Ω
8305AGI
www.idt.com
2
REV. B JULY 29, 2010
ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
OE
1
1
1
1
CLK_EN
0
0
1
1
Inputs
CLK_SEL
0
1
0
1
Selected Source
LVCMOS_CLK
CLK, nCLK
LVCMOS_CLK
CLK, nCLK
Outputs
Q0:Q3
Disabled; LOW
Disabled; LOW
Enabled
Enabled
0
X
X
Hi Z
NOTE: After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
Disabled
Enabled
nCLK
CLK,
LVCMOS_CLK
CLK_EN
Q0:Q3
F
IGURE
1. CLK_EN T
IMING
D
IAGRAM
8305AGI
www.idt.com
3
REV. B JULY 29, 2010
ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
89°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
2.375
1.65
Typical
3.3
3.3
2.5
1.8
Maximum
3.465
3.465
2.625
1.95
21
5
Units
V
V
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
V
IH
V
IL
I
IH
I
IL
Input
High Voltage
Input
Low Voltage
Input
High Current
Input
Low Current
CLK_EN, CLK_SEL, OE
LVCMOS_CLK
CLK_EN, CLK_SEL, OE
LVCMOS_CLK
CLK_EN, CLK_SEL, OE
LVCMOS_CLK
CLK_EN, CLK_SEL, OE
LVCMOS_CLK
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
V
DDO
= 3.3V ± 5%
V
OH
Output High Voltage; NOTE 1
V
DDO
= 2.5V ± 5%
V
DDO
= 1.8V ± 0.15V
V
DDO
= 3.3V ± 5%
V
OL
I
OZL
I
OZH
Output Low Voltage; NOTE 1
Output Tristate Current Low
Output Tristate Current High
V
DDO
= 2.5V ± 5%
V
DDO
= 1.8V ± 0.15V
-5
5
-150
-5
2.6
1.8
V
DDO
- 0.3
0.5
0.5
0.4
Test Conditions
Minimum Typical
2
2
-0.3
-0.3
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.3
5
150
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
V
V
µA
µA
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement Information, Output Load Test Circuit.
8305AGI
www.idt.com
4
REV. B JULY 29, 2010
ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
nCLK
CLK
nCLK
CLK
Test Conditions
V
IN
= V
DD
= 3.465V
V
IN
= V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
-150
-5
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
150
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
V
CMR
GND + 0.5
NOTE 1, 2
NOTE 1: For single ended applications
,
the maximum input voltage for CLK, nCLK is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
Output Frequency
LVCMOS_CLK;
Propagation Delay, NOTE 1A
Low to High
CLK, nCLK;
NOTE 1B
Output Skew; NOTE 2, 6
Par t-to-Par t Skew; NOTE 3, 6
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 5
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 4
Test Conditions
Ref = CLK/nCLK
Ref = LVCMOS_CLK
1.75
Measured on the Rising Edge
Minimum
Typical
Maximum
350
300
2.8
40
700
0.04
20% to 80%
IJ 200MHz
ƒ > 200MHz
100
45
42
700
55
58
5
5
Units
MHz
MHz
ns
ps
ps
ps
ps
%
%
ns
ns
tp
LH
t
sk(o)
t
sk(pp)
t
jit
t
R
/ t
F
odc
t
EN
Output Disable Time; NOTE 4
t
DIS
NOTE 1A: Measured from the V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 1B: Measured from the differential input crossing point to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Driving only one input clock.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
8305AGI
www.idt.com
5
REV. B JULY 29, 2010
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