CAT24WC66
64-Kb I
2
C Serial EEPROM
with Partial Array Write
Protection
Description
The CAT24WC66 is a 64−Kb Serial CMOS EEPROM internally
organized as 8192 words of 8 bits each. ON Semiconductor’s
advanced CMOS technology substantially reduces device power
requirements. The CAT24WC66 features a 32−byte page write buffer.
The device operates via the I
2
C bus serial interface and is available in
8−pin PDIP or 8−pin SOIC packages.
Features
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400 kHz
Bus
1.8 V to 5.5 V Supply Voltage Range
Cascadable for up to Eight Devices
32−byte Page Write Buffer
Self−timed Write Cycle with Auto−clear
Schmitt Trigger Inputs for Noise Protection
Write Protection
−
Top 1/4 Array Protected when WP at V
IH
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Automotive Temperature Ranges
This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
V
CC
I
2
C
PDIP−8
L SUFFIX
CASE 646AA
SOIC−8
W or X SUFFIX
CASE 751BD
PIN CONFIGURATIONS
A
0
A
1
A
2
V
SS
DIP Package (L)
A
0
A
1
A
2
V
SS
1
V
CC
WP
SCL
SDA
SOIC Package (W, X)
1
V
CC
WP
SCL
SDA
SCL
A
2
, A
1
, A
0
WP
CAT24CW66
SDA
PIN FUNCTION
Pin Name
A0, A1, A2
SDA
SCL
Function
Device Address Inputs
Serial Data/Address
Serial Clock
Write Protect
Power Supply
Ground
V
SS
WP
V
CC
V
SS
Figure 1. Functional Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
©
Semiconductor Components Industries, LLC, 2009
August, 2009
−
Rev. 10
1
Publication Order Number:
CAT24WC66/D
CAT24WC66
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25°C)
Lead Soldering Temperature (10 secs)
Output Short Circuit Current (Note 2)
Ratings
–55 to +125
–65 to +150
–2.0 to V
CC
+ 2.0
–2.0 to 7.0
1.0
300
100
Units
°C
°C
V
V
W
°C
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods of less than 20 ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 2. REABILITY CHARACTERISTICS
Symbol
NEND
(Note 3)
TDR
(Note 3)
VZAP
(Note 3)
ILTH
(Notes 3, 4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch−up
Reference Test Method
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Max
Units
Cycles / Byte
Years
Volts
mA
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from –1 V to V
CC
+ 1 V.
Table 3. D.C. OPERATING CHARACTERISTICS
(V
CC
= 1.8 V to 5.5 V, unless otherwise specified.)
Symbol
I
CC
I
SB
(Note 5)
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
Parameter
Power Supply Current
Standby Current (V
CC
= 5 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= +3.0 V)
Output Low Voltage(V
CC
= +1.8 V)
I
OL
= 3.0 mA
I
OL
= 1.5 mA
Test Conditions
f
SCL
= 100 kHz
V
IN
= GND or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
−1
V
CC
x 0.7
Min
Typ
Max
3
1
10
10
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.5
Units
mA
mA
mA
mA
V
V
V
V
5. Maximum standby current (ISB) = 10
mA
for the Automotive and Extended Automotive temperature range.
Table 4. CAPACITANCE
(T
A
= 25°C, f = 1.0 MHz, V
CC
= 5 V)
Symbol
C
I/O
(Note 3)
C
IN
(Note 3)
Parameter
Input/Output Capacitance (SDA)
Input Capacitance
(A0, A1, A2, SCL, WP)
Conditions
V
I/O
= 0 V
V
IN
= 0 V
Min
Typ
Max
8
6
Units
pF
pF
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CAT24WC66
Table 5.
A.C. CHARACTERISTICS
(
V
CC
= 1.8 V to 5.5 V, unless otherwise specified. Output Load is 1TTL Gate and 100 pF.)
1.8 V
−
2.5 V
Symbol
Parameter
Min
Max
4.5 V
−
5.5 V
Min
Max
Units
MEMORY READ & WRITE CYCLE LIMITS
FSCL
T
I
(Note 6)
t
AA
t
BUF
(Note 6)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
(Note 6)
t
F
(Note 6)
t
SU:STO
t
DH
Clock Frequency
Noise Suppression Time Constant at
SCL, SDA Inputs
SCL Low to SDA Data Out and ACK Out
Time the Bus Must be Free Before a
New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
4
100
4.7
4
4.7
4
4.7
0
50
1
300
0.6
100
100
200
3.5
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
400
200
1
kHz
ns
ms
ms
ms
ms
ms
ms
ns
ns
ms
ns
ms
ns
6. This parameter is tested initially and after a design or process change that affects the parameter.
Table 6. POWER−UP TIMING
(Notes 6, 7)
Symbol
t
PUR
t
PUW
Parameter
Power−Up to Read Operation
Power−Up to Write Operation
Min
Typ
Max
1
1
Units
ms
ms
7. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Table 7. WRITE CYCLE LIMITS
Symbol
t
WR
Write Cycle Time
Parameter
Min
Typ
Max
10
Units
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond
to its slave address.
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CAT24WC66
Functional Description
The CAT24WC66 supports the I
2
C Bus data transmission
protocol. This Inter−Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter and
any device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the serial
clock and all START and STOP conditions for bus access.
The CAT24WC66 operates as a Slave device. Both the
Master device and Slave device can operate as either
transmitter or receiver, but the Master device controls which
mode is activated.
Pin Description
SCL:
Serial Clock
The serial clock input clocks all data transferred into or out
of the device.
SDA:
Serial Data/Address
t
F
t
LOW
SCL
t
SU:STA
SDA IN
t
AA
SDA OUT
t
DH
t
BUF
t
HD:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
HIGH
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs.
A0, A1, A2:
Device Address Inputs
These pins are hardwired or left unconnected (for
hardware compatibility with CAT24WC16). When
hardwired, up to eight CAT24WC66 devices may be
addressed on a single bus system (refer to Device
Addressing). When the pins are left unconnected, the default
values are zeros.
WP:
Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to V
CC
, the top 1/4
array of memory is write protected. When left floating,
memory is unprotected.
t
R
t
LOW
Figure 2. Bus Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Write Cycle Timing
SDA
SCL
START BIT
STOP BIT
Figure 4. Start/Stop Timing
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CAT24WC66
I
2
C Bus Protocol
The features of the I
2
C bus protocol are defined as
follows:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition.
START Condition
specifies whether a Read or Write operation is to be
performed. When this bit is set to 1, a Read operation is
selected, and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC66 monitors the bus and
responds with an acknowledge (on the SDA line) when its
address matches the transmitted slave address. The
CAT24WC66 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT24WC66 monitors the SDA
and SCL lines and will not respond until this condition is
met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8−bit slave address are fixed as 1010
(Figure 6). The next three bits (A2, A1, A0) are the device
address bits; up to eight 64K devices may to be connected to
the same bus. These bits must compare to the hardwired
input pins, A2, A1 and A0. The last bit of the slave address
SCL FROM
MASTER
1
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
The CAT24WC66 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8−bit
byte.
When the CAT24WC66 begins a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the line
for an acknowledge. Once it receives this acknowledge, the
CAT24WC66 will continue to transmit data. If no
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition. The
master must then issue a stop condition to return the
CAT24WC66 to the standby power mode and place the
device in a known state.
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Acknowledge Timing
1
0
1
0
A2
A1
A0
R/W
DEVICE ADDRESS
Figure 6. Slave Address Bits
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